242 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek AFE PCM controller for mt81888 9maintainers:10 - Trevor Wu <trevor.wu@mediatek.com>11 12properties:13 compatible:14 const: mediatek,mt8188-afe15 16 reg:17 maxItems: 118 19 interrupts:20 maxItems: 121 22 resets:23 maxItems: 124 25 reset-names:26 const: audiosys27 28 memory-region:29 maxItems: 130 description: |31 Shared memory region for AFE memif. A "shared-dma-pool".32 See dtschema reserved-memory/shared-dma-pool.yaml for details.33 34 mediatek,topckgen:35 $ref: /schemas/types.yaml#/definitions/phandle36 description: The phandle of the mediatek topckgen controller37 38 mediatek,infracfg:39 $ref: /schemas/types.yaml#/definitions/phandle40 description: The phandle of the mediatek infracfg controller41 42 power-domains:43 maxItems: 144 45 clocks:46 items:47 - description: 26M clock48 - description: audio pll1 clock49 - description: audio pll2 clock50 - description: clock divider for i2si1_mck51 - description: clock divider for i2si2_mck52 - description: clock divider for i2so1_mck53 - description: clock divider for i2so2_mck54 - description: clock divider for dptx_mck55 - description: a1sys hoping clock56 - description: audio intbus clock57 - description: audio hires clock58 - description: audio local bus clock59 - description: mux for dptx_mck60 - description: mux for i2so1_mck61 - description: mux for i2so2_mck62 - description: mux for i2si1_mck63 - description: mux for i2si2_mck64 - description: audio 26m clock65 - description: audio pll1 divide 466 - description: audio pll2 divide 467 - description: clock divider for iec68 - description: mux for a2sys clock69 - description: mux for aud_iec70 71 clock-names:72 items:73 - const: clk26m74 - const: apll175 - const: apll276 - const: apll12_div077 - const: apll12_div178 - const: apll12_div279 - const: apll12_div380 - const: apll12_div981 - const: top_a1sys_hp82 - const: top_aud_intbus83 - const: top_audio_h84 - const: top_audio_local_bus85 - const: top_dptx86 - const: top_i2so187 - const: top_i2so288 - const: top_i2si189 - const: top_i2si290 - const: adsp_audio_26m91 - const: apll1_d492 - const: apll2_d493 - const: apll12_div494 - const: top_a2sys95 - const: top_aud_iec96 97 mediatek,etdm-in1-cowork-source:98 $ref: /schemas/types.yaml#/definitions/uint3299 description:100 etdm modules can share the same external clock pin. Specify101 which etdm clock source is required by this etdm in module.102 enum:103 - 1 # etdm2_in104 - 2 # etdm1_out105 - 3 # etdm2_out106 107 mediatek,etdm-in2-cowork-source:108 $ref: /schemas/types.yaml#/definitions/uint32109 description:110 etdm modules can share the same external clock pin. Specify111 which etdm clock source is required by this etdm in module.112 enum:113 - 0 # etdm1_in114 - 2 # etdm1_out115 - 3 # etdm2_out116 117 mediatek,etdm-out1-cowork-source:118 $ref: /schemas/types.yaml#/definitions/uint32119 description:120 etdm modules can share the same external clock pin. Specify121 which etdm clock source is required by this etdm out module.122 enum:123 - 0 # etdm1_in124 - 1 # etdm2_in125 - 3 # etdm2_out126 127 mediatek,etdm-out2-cowork-source:128 $ref: /schemas/types.yaml#/definitions/uint32129 description:130 etdm modules can share the same external clock pin. Specify131 which etdm clock source is required by this etdm out module.132 enum:133 - 0 # etdm1_in134 - 1 # etdm2_in135 - 2 # etdm1_out136 137patternProperties:138 "^mediatek,etdm-in[1-2]-chn-disabled$":139 $ref: /schemas/types.yaml#/definitions/uint8-array140 minItems: 1141 maxItems: 16142 description:143 This is a list of channel IDs which should be disabled.144 By default, all data received from ETDM pins will be outputted to145 memory. etdm in supports disable_out in direct mode(w/o interconn),146 so user can disable the specified channels by the property.147 uniqueItems: true148 items:149 minimum: 0150 maximum: 15151 152 "^mediatek,etdm-in[1-2]-multi-pin-mode$":153 type: boolean154 description: if present, the etdm data mode is I2S.155 156 "^mediatek,etdm-out[1-3]-multi-pin-mode$":157 type: boolean158 description: if present, the etdm data mode is I2S.159 160required:161 - compatible162 - reg163 - interrupts164 - resets165 - reset-names166 - mediatek,topckgen167 - mediatek,infracfg168 - power-domains169 - clocks170 - clock-names171 172additionalProperties: false173 174examples:175 - |176 #include <dt-bindings/interrupt-controller/arm-gic.h>177 #include <dt-bindings/interrupt-controller/irq.h>178 179 afe@10b10000 {180 compatible = "mediatek,mt8188-afe";181 reg = <0x10b10000 0x10000>;182 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;183 resets = <&watchdog 14>;184 reset-names = "audiosys";185 memory-region = <&snd_dma_mem_reserved>;186 mediatek,topckgen = <&topckgen>;187 mediatek,infracfg = <&infracfg_ao>;188 power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO189 mediatek,etdm-in2-cowork-source = <2>;190 mediatek,etdm-out2-cowork-source = <0>;191 mediatek,etdm-in1-multi-pin-mode;192 mediatek,etdm-in1-chn-disabled = /bits/ 8 <0x0 0x2>;193 clocks = <&clk26m>,194 <&apmixedsys 9>, //CLK_APMIXED_APLL1195 <&apmixedsys 10>, //CLK_APMIXED_APLL2196 <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0197 <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1198 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2199 <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3200 <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9201 <&topckgen 83>, //CLK_TOP_A1SYS_HP202 <&topckgen 31>, //CLK_TOP_AUD_INTBUS203 <&topckgen 32>, //CLK_TOP_AUDIO_H204 <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS205 <&topckgen 81>, //CLK_TOP_DPTX206 <&topckgen 77>, //CLK_TOP_I2SO1207 <&topckgen 78>, //CLK_TOP_I2SO2208 <&topckgen 79>, //CLK_TOP_I2SI1209 <&topckgen 80>, //CLK_TOP_I2SI2210 <&adsp_audio26m 0>, //CLK_AUDIODSP_AUDIO26M211 <&topckgen 132>, //CLK_TOP_APLL1_D4212 <&topckgen 133>, //CLK_TOP_APLL2_D4213 <&topckgen 183>, //CLK_TOP_APLL12_CK_DIV4214 <&topckgen 84>, //CLK_TOP_A2SYS215 <&topckgen 82>; //CLK_TOP_AUD_IEC>;216 clock-names = "clk26m",217 "apll1",218 "apll2",219 "apll12_div0",220 "apll12_div1",221 "apll12_div2",222 "apll12_div3",223 "apll12_div9",224 "top_a1sys_hp",225 "top_aud_intbus",226 "top_audio_h",227 "top_audio_local_bus",228 "top_dptx",229 "top_i2so1",230 "top_i2so2",231 "top_i2si1",232 "top_i2si2",233 "adsp_audio_26m",234 "apll1_d4",235 "apll2_d4",236 "apll12_div4",237 "top_a2sys",238 "top_aud_iec";239 };240 241...242