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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Mediatek AFE PCM controller for mt81868 9maintainers:10 - Jiaxin Yu <jiaxin.yu@mediatek.com>11 12properties:13 compatible:14 const: mediatek,mt8186-sound15 16 reg:17 maxItems: 118 19 interrupts:20 maxItems: 121 22 resets:23 maxItems: 124 25 reset-names:26 const: audiosys27 28 mediatek,apmixedsys:29 $ref: /schemas/types.yaml#/definitions/phandle30 description: The phandle of the mediatek apmixedsys controller31 32 mediatek,infracfg:33 $ref: /schemas/types.yaml#/definitions/phandle34 description: The phandle of the mediatek infracfg controller35 36 mediatek,topckgen:37 $ref: /schemas/types.yaml#/definitions/phandle38 description: The phandle of the mediatek topckgen controller39 40 clocks:41 items:42 - description: audio infra sys clock43 - description: audio infra 26M clock44 - description: audio top mux45 - description: audio intbus mux46 - description: mainpll 136.5M clock47 - description: faud1 mux48 - description: apll1 clock49 - description: faud2 mux50 - description: apll2 clock51 - description: audio engen1 mux52 - description: apll1_d8 22.5792M clock53 - description: audio engen2 mux54 - description: apll2_d8 24.576M clock55 - description: i2s0 mclk mux56 - description: i2s1 mclk mux57 - description: i2s2 mclk mux58 - description: i2s4 mclk mux59 - description: tdm mclk mux60 - description: i2s0_mck divider61 - description: i2s1_mck divider62 - description: i2s2_mck divider63 - description: i2s4_mck divider64 - description: tdm_mck divider65 - description: audio hires mux66 - description: 26M clock67 68 clock-names:69 items:70 - const: aud_infra_clk71 - const: mtkaif_26m_clk72 - const: top_mux_audio73 - const: top_mux_audio_int74 - const: top_mainpll_d2_d475 - const: top_mux_aud_176 - const: top_apll1_ck77 - const: top_mux_aud_278 - const: top_apll2_ck79 - const: top_mux_aud_eng180 - const: top_apll1_d881 - const: top_mux_aud_eng282 - const: top_apll2_d883 - const: top_i2s0_m_sel84 - const: top_i2s1_m_sel85 - const: top_i2s2_m_sel86 - const: top_i2s4_m_sel87 - const: top_tdm_m_sel88 - const: top_apll12_div089 - const: top_apll12_div190 - const: top_apll12_div291 - const: top_apll12_div492 - const: top_apll12_div_tdm93 - const: top_mux_audio_h94 - const: top_clk26m_clk95 96required:97 - compatible98 - interrupts99 - resets100 - reset-names101 - mediatek,apmixedsys102 - mediatek,infracfg103 - mediatek,topckgen104 - clocks105 - clock-names106 107additionalProperties: false108 109examples:110 - |111 #include <dt-bindings/interrupt-controller/arm-gic.h>112 #include <dt-bindings/interrupt-controller/irq.h>113 114 afe: mt8186-afe-pcm@11210000 {115 compatible = "mediatek,mt8186-sound";116 reg = <0x11210000 0x2000>;117 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;118 resets = <&watchdog 17>; //MT8186_TOPRGU_AUDIO_SW_RST119 reset-names = "audiosys";120 mediatek,apmixedsys = <&apmixedsys>;121 mediatek,infracfg = <&infracfg>;122 mediatek,topckgen = <&topckgen>;123 clocks = <&infracfg_ao 44>, //CLK_INFRA_AO_AUDIO124 <&infracfg_ao 54>, //CLK_INFRA_AO_AUDIO_26M_BCLK125 <&topckgen 15>, //CLK_TOP_AUDIO126 <&topckgen 16>, //CLK_TOP_AUD_INTBUS127 <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4128 <&topckgen 17>, //CLK_TOP_AUD_1129 <&apmixedsys 12>, //CLK_APMIXED_APLL1130 <&topckgen 18>, //CLK_TOP_AUD_2131 <&apmixedsys 13>, //CLK_APMIXED_APLL2132 <&topckgen 19>, //CLK_TOP_AUD_ENGEN1133 <&topckgen 101>, //CLK_TOP_APLL1_D8134 <&topckgen 20>, //CLK_TOP_AUD_ENGEN2135 <&topckgen 104>, //CLK_TOP_APLL2_D8136 <&topckgen 63>, //CLK_TOP_APLL_I2S0_MCK_SEL137 <&topckgen 64>, //CLK_TOP_APLL_I2S1_MCK_SEL138 <&topckgen 65>, //CLK_TOP_APLL_I2S2_MCK_SEL139 <&topckgen 66>, //CLK_TOP_APLL_I2S4_MCK_SEL140 <&topckgen 67>, //CLK_TOP_APLL_TDMOUT_MCK_SEL141 <&topckgen 131>, //CLK_TOP_APLL12_CK_DIV0142 <&topckgen 132>, //CLK_TOP_APLL12_CK_DIV1143 <&topckgen 133>, //CLK_TOP_APLL12_CK_DIV2144 <&topckgen 134>, //CLK_TOP_APLL12_CK_DIV4145 <&topckgen 135>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M146 <&topckgen 44>, //CLK_TOP_AUDIO_H147 <&clk26m>;148 clock-names = "aud_infra_clk",149 "mtkaif_26m_clk",150 "top_mux_audio",151 "top_mux_audio_int",152 "top_mainpll_d2_d4",153 "top_mux_aud_1",154 "top_apll1_ck",155 "top_mux_aud_2",156 "top_apll2_ck",157 "top_mux_aud_eng1",158 "top_apll1_d8",159 "top_mux_aud_eng2",160 "top_apll2_d8",161 "top_i2s0_m_sel",162 "top_i2s1_m_sel",163 "top_i2s2_m_sel",164 "top_i2s4_m_sel",165 "top_tdm_m_sel",166 "top_apll12_div0",167 "top_apll12_div1",168 "top_apll12_div2",169 "top_apll12_div4",170 "top_apll12_div_tdm",171 "top_mux_audio_h",172 "top_clk26m_clk";173 };174 175...176