201 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Mediatek AFE PCM controller for mt81958 9maintainers:10 - Trevor Wu <trevor.wu@mediatek.com>11 12properties:13 compatible:14 const: mediatek,mt8195-audio15 16 reg:17 maxItems: 118 19 interrupts:20 maxItems: 121 22 resets:23 maxItems: 124 25 reset-names:26 const: audiosys27 28 memory-region:29 maxItems: 130 description: |31 Shared memory region for AFE memif. A "shared-dma-pool".32 See ../reserved-memory/reserved-memory.txt for details.33 34 mediatek,topckgen:35 $ref: /schemas/types.yaml#/definitions/phandle36 description: The phandle of the mediatek topckgen controller37 38 power-domains:39 maxItems: 140 41 clocks:42 items:43 - description: 26M clock44 - description: audio pll1 clock45 - description: audio pll2 clock46 - description: clock divider for i2si1_mck47 - description: clock divider for i2si2_mck48 - description: clock divider for i2so1_mck49 - description: clock divider for i2so2_mck50 - description: clock divider for dptx_mck51 - description: a1sys hoping clock52 - description: audio intbus clock53 - description: audio hires clock54 - description: audio local bus clock55 - description: mux for dptx_mck56 - description: mux for i2so1_mck57 - description: mux for i2so2_mck58 - description: mux for i2si1_mck59 - description: mux for i2si2_mck60 - description: audio infra 26M clock61 - description: infra bus clock62 63 clock-names:64 items:65 - const: clk26m66 - const: apll1_ck67 - const: apll2_ck68 - const: apll12_div069 - const: apll12_div170 - const: apll12_div271 - const: apll12_div372 - const: apll12_div973 - const: a1sys_hp_sel74 - const: aud_intbus_sel75 - const: audio_h_sel76 - const: audio_local_bus_sel77 - const: dptx_m_sel78 - const: i2so1_m_sel79 - const: i2so2_m_sel80 - const: i2si1_m_sel81 - const: i2si2_m_sel82 - const: infra_ao_audio_26m_b83 - const: scp_adsp_audiodsp84 85 mediatek,etdm-in1-chn-disabled:86 $ref: /schemas/types.yaml#/definitions/uint8-array87 maxItems: 2488 description: Specify which input channel should be disabled.89 90 mediatek,etdm-in2-chn-disabled:91 $ref: /schemas/types.yaml#/definitions/uint8-array92 maxItems: 1693 description: Specify which input channel should be disabled.94 95patternProperties:96 "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":97 description: Specify etdm in mclk output rate for always on case.98 99 "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":100 description: Specify etdm out mclk output rate for always on case.101 102 "^mediatek,etdm-in[1-2]-multi-pin-mode$":103 type: boolean104 description: if present, the etdm data mode is I2S.105 106 "^mediatek,etdm-out[1-3]-multi-pin-mode$":107 type: boolean108 description: if present, the etdm data mode is I2S.109 110 "^mediatek,etdm-in[1-2]-cowork-source$":111 $ref: /schemas/types.yaml#/definitions/uint32112 description: |113 etdm modules can share the same external clock pin. Specify114 which etdm clock source is required by this etdm in module.115 enum:116 - 0 # etdm1_in117 - 1 # etdm2_in118 - 2 # etdm1_out119 - 3 # etdm2_out120 121 "^mediatek,etdm-out[1-2]-cowork-source$":122 $ref: /schemas/types.yaml#/definitions/uint32123 description: |124 etdm modules can share the same external clock pin. Specify125 which etdm clock source is required by this etdm out module.126 enum:127 - 0 # etdm1_in128 - 1 # etdm2_in129 - 2 # etdm1_out130 - 3 # etdm2_out131 132required:133 - compatible134 - reg135 - interrupts136 - resets137 - reset-names138 - mediatek,topckgen139 - power-domains140 - clocks141 - clock-names142 - memory-region143 144additionalProperties: false145 146examples:147 - |148 #include <dt-bindings/interrupt-controller/arm-gic.h>149 #include <dt-bindings/interrupt-controller/irq.h>150 151 afe: mt8195-afe-pcm@10890000 {152 compatible = "mediatek,mt8195-audio";153 reg = <0x10890000 0x10000>;154 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;155 resets = <&watchdog 14>;156 reset-names = "audiosys";157 mediatek,topckgen = <&topckgen>;158 power-domains = <&spm 7>; //MT8195_POWER_DOMAIN_AUDIO159 memory-region = <&snd_dma_mem_reserved>;160 clocks = <&clk26m>,161 <&topckgen 163>, //CLK_TOP_APLL1162 <&topckgen 166>, //CLK_TOP_APLL2163 <&topckgen 233>, //CLK_TOP_APLL12_DIV0164 <&topckgen 234>, //CLK_TOP_APLL12_DIV1165 <&topckgen 235>, //CLK_TOP_APLL12_DIV2166 <&topckgen 236>, //CLK_TOP_APLL12_DIV3167 <&topckgen 238>, //CLK_TOP_APLL12_DIV9168 <&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL169 <&topckgen 33>, //CLK_TOP_AUD_INTBUS_SEL170 <&topckgen 34>, //CLK_TOP_AUDIO_H_SEL171 <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS_SEL172 <&topckgen 98>, //CLK_TOP_DPTX_M_SEL173 <&topckgen 94>, //CLK_TOP_I2SO1_M_SEL174 <&topckgen 95>, //CLK_TOP_I2SO2_M_SEL175 <&topckgen 96>, //CLK_TOP_I2SI1_M_SEL176 <&topckgen 97>, //CLK_TOP_I2SI2_M_SEL177 <&infracfg_ao 50>, //CLK_INFRA_AO_AUDIO_26M_B178 <&scp_adsp 0>; //CLK_SCP_ADSP_AUDIODSP179 clock-names = "clk26m",180 "apll1_ck",181 "apll2_ck",182 "apll12_div0",183 "apll12_div1",184 "apll12_div2",185 "apll12_div3",186 "apll12_div9",187 "a1sys_hp_sel",188 "aud_intbus_sel",189 "audio_h_sel",190 "audio_local_bus_sel",191 "dptx_m_sel",192 "i2so1_m_sel",193 "i2so2_m_sel",194 "i2si1_m_sel",195 "i2si2_m_sel",196 "infra_ao_audio_26m_b",197 "scp_adsp_audiodsp";198 };199 200...201