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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-max9808x.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra audio complex with MAX9808x CODEC8 9maintainers:10 - Jon Hunter <jonathanh@nvidia.com>11 - Thierry Reding <thierry.reding@gmail.com>12 13allOf:14 - $ref: nvidia,tegra-audio-common.yaml#15 16properties:17 compatible:18 oneOf:19 - items:20 - pattern: '^[a-z0-9]+,tegra-audio-max98088(-[a-z0-9]+)+$'21 - const: nvidia,tegra-audio-max9808822 - items:23 - pattern: '^[a-z0-9]+,tegra-audio-max98089(-[a-z0-9]+)+$'24 - const: nvidia,tegra-audio-max9808925 26 nvidia,audio-routing:27 $ref: /schemas/types.yaml#/definitions/non-unique-string-array28 description: |29 A list of the connections between audio components.30 Each entry is a pair of strings, the first being the connection's sink,31 the second being the connection's source. Valid names for sources and32 sinks are the pins (documented in the binding document),33 and the jacks on the board.34 minItems: 235 items:36 enum:37 # Board Connectors38 - Int Spk39 - Headphone Jack40 - Earpiece41 - Headset Mic42 - Internal Mic 143 - Internal Mic 244 45 # CODEC Pins46 - HPL47 - HPR48 - SPKL49 - SPKR50 - RECL51 - RECR52 - INA153 - INA254 - INB155 - INB256 - MIC157 - MIC258 - MICBIAS59 60unevaluatedProperties: false61 62examples:63 - |64 #include <dt-bindings/clock/tegra30-car.h>65 #include <dt-bindings/soc/tegra-pmc.h>66 sound {67 compatible = "lg,tegra-audio-max98089-p895",68 "nvidia,tegra-audio-max98089";69 nvidia,model = "LG Optimus Vu MAX98089";70 71 nvidia,audio-routing =72 "Headphone Jack", "HPL",73 "Headphone Jack", "HPR",74 "Int Spk", "SPKL",75 "Int Spk", "SPKR",76 "Earpiece", "RECL",77 "Earpiece", "RECR",78 "INA1", "Headset Mic",79 "MIC1", "MICBIAS",80 "MICBIAS", "Internal Mic 1",81 "MIC2", "Internal Mic 2";82 83 nvidia,i2s-controller = <&tegra_i2s0>;84 nvidia,audio-codec = <&codec>;85 86 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,87 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,88 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;89 clock-names = "pll_a", "pll_a_out0", "mclk";90 };91