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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra20 S/PDIF Controller8 9description: |10 The S/PDIF controller supports both input and output in serial audio11 digital interface format. The input controller can digitally recover12 a clock from the received stream. The S/PDIF controller is also used13 to generate the embedded audio for HDMI output channel.14 15maintainers:16 - Thierry Reding <treding@nvidia.com>17 - Jon Hunter <jonathanh@nvidia.com>18 19allOf:20 - $ref: dai-common.yaml#21 22properties:23 compatible:24 const: nvidia,tegra20-spdif25 26 reg:27 maxItems: 128 29 resets:30 maxItems: 131 32 interrupts:33 maxItems: 134 35 clocks:36 minItems: 237 38 clock-names:39 items:40 - const: out41 - const: in42 43 dmas:44 minItems: 245 46 dma-names:47 items:48 - const: rx49 - const: tx50 51 "#sound-dai-cells":52 const: 053 54 nvidia,fixed-parent-rate:55 description: |56 Specifies whether board prefers parent clock to stay at a fixed rate.57 This allows multiple Tegra20 audio components work simultaneously by58 limiting number of supportable audio rates.59 type: boolean60 61required:62 - compatible63 - reg64 - resets65 - interrupts66 - clocks67 - clock-names68 - dmas69 - dma-names70 - "#sound-dai-cells"71 72unevaluatedProperties: false73 74examples:75 - |76 spdif@70002400 {77 compatible = "nvidia,tegra20-spdif";78 reg = <0x70002400 0x200>;79 interrupts = <77>;80 clocks = <&clk 99>, <&clk 98>;81 clock-names = "out", "in";82 resets = <&rst 10>;83 dmas = <&apbdma 3>, <&apbdma 3>;84 dma-names = "rx", "tx";85 #sound-dai-cells = <0>;86 };87 88...89