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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)8 9maintainers:10 - Biju Das <biju.das.jz@bp.renesas.com>11 12allOf:13 - $ref: dai-common.yaml#14 15properties:16 compatible:17 items:18 - enum:19 - renesas,r9a07g043-ssi # RZ/G2UL and RZ/Five20 - renesas,r9a07g044-ssi # RZ/G2{L,LC}21 - renesas,r9a07g054-ssi # RZ/V2L22 - const: renesas,rz-ssi23 24 reg:25 maxItems: 126 27 interrupts:28 minItems: 229 maxItems: 330 31 interrupt-names:32 oneOf:33 - items:34 - const: int_req35 - const: dma_rx36 - const: dma_tx37 - items:38 - const: int_req39 - const: dma_rt40 41 clocks:42 maxItems: 443 44 clock-names:45 items:46 - const: ssi47 - const: ssi_sfr48 - const: audio_clk149 - const: audio_clk250 51 power-domains:52 maxItems: 153 54 resets:55 maxItems: 156 57 dmas:58 minItems: 159 maxItems: 260 description:61 The first cell represents a phandle to dmac.62 The second cell specifies the encoded MID/RID values of the SSI port63 connected to the DMA client and the slave channel configuration64 parameters.65 bits[0:9] - Specifies MID/RID value of a SSI channel as below66 MID/RID value of SSI rx0 = 0x25667 MID/RID value of SSI tx0 = 0x25568 MID/RID value of SSI rx1 = 0x25a69 MID/RID value of SSI tx1 = 0x25970 MID/RID value of SSI rt2 = 0x25f71 MID/RID value of SSI rx3 = 0x26272 MID/RID value of SSI tx3 = 0x26173 bit[10] - HIEN = 1, Detects a request in response to the rising edge74 of the signal75 bit[11] - LVL = 0, Detects based on the edge76 bits[12:14] - AM = 2, Bus cycle mode77 bit[15] - TM = 0, Single transfer mode78 79 dma-names:80 oneOf:81 - items:82 - const: tx83 - const: rx84 - items:85 - const: rt86 87 '#sound-dai-cells':88 const: 089 90 port:91 $ref: audio-graph-port.yaml#/definitions/port-base92 description: Connection to controller providing I2S signals93 94required:95 - compatible96 - reg97 - interrupts98 - interrupt-names99 - clocks100 - clock-names101 - resets102 - '#sound-dai-cells'103 104unevaluatedProperties: false105 106examples:107 - |108 #include <dt-bindings/interrupt-controller/arm-gic.h>109 #include <dt-bindings/clock/r9a07g044-cpg.h>110 111 ssi0: ssi@10049c00 {112 compatible = "renesas,r9a07g044-ssi",113 "renesas,rz-ssi";114 reg = <0x10049c00 0x400>;115 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,116 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,117 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;118 interrupt-names = "int_req", "dma_rx", "dma_tx";119 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,120 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,121 <&audio_clk1>,122 <&audio_clk2>;123 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";124 power-domains = <&cpg>;125 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;126 dmas = <&dmac 0x2655>,127 <&dmac 0x2656>;128 dma-names = "tx", "rx";129 #sound-dai-cells = <0>;130 };131