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1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)2# Copyright (C) 2019 Texas Instruments Incorporated3%YAML 1.24---5$id: http://devicetree.org/schemas/sound/ti,tlv320adcx140.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter9 10maintainers:11 - Andrew Davis <afd@ti.com>12 13description: |14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital15 PDM microphones recording), high-performance audio, analog-to-digital16 converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX14017 family supports line and microphone Inputs, and offers a programmable18 microphone bias or supply voltage generation.19 20 Specifications can be found at:21 https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf22 https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf23 https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf24 25properties:26 compatible:27 enum:28 - ti,tlv320adc314029 - ti,tlv320adc514030 - ti,tlv320adc614031 32 reg:33 maxItems: 134 description: |35 I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f36 37 reset-gpios:38 maxItems: 139 description: |40 GPIO used for hardware reset.41 42 areg-supply:43 description: |44 Regulator with AVDD at 3.3V. If not defined then the internal regulator45 is enabled.46 47 ti,mic-bias-source:48 description: |49 Indicates the source for MIC Bias.50 0 - Mic bias is set to VREF51 1 - Mic bias is set to VREF × 1.09652 6 - Mic bias is set to AVDD53 $ref: /schemas/types.yaml#/definitions/uint3254 enum: [0, 1, 6]55 56 ti,vref-source:57 description: |58 Indicates the source for MIC Bias.59 0 - Set VREF to 2.75V60 1 - Set VREF to 2.5V61 2 - Set VREF to 1.375V62 $ref: /schemas/types.yaml#/definitions/uint3263 enum: [0, 1, 2]64 65 ti,pdm-edge-select:66 description: |67 Defines the PDMCLK sampling edge configuration for the PDM inputs. This68 array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.69 70 0 - (default) Odd channel is latched on the negative edge and even71 channel is latched on the positive edge.72 1 - Odd channel is latched on the positive edge and even channel is73 latched on the negative edge.74 75 PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data76 PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data77 PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data78 PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data79 80 $ref: /schemas/types.yaml#/definitions/uint32-array81 minItems: 182 maxItems: 483 items:84 maximum: 185 default: [0, 0, 0, 0]86 87 ti,gpi-config:88 description: |89 Defines the configuration for the general purpose input pins (GPI).90 The array is defined as <GPI1 GPI2 GPI3 GPI4>.91 92 0 - (default) disabled93 1 - GPIX is configured as a general-purpose input (GPI)94 2 - GPIX is configured as a master clock input (MCLK)95 3 - GPIX is configured as an ASI input for daisy-chain (SDIN)96 4 - GPIX is configured as a PDM data input for channel 1 and channel97 (PDMDIN1)98 5 - GPIX is configured as a PDM data input for channel 3 and channel99 (PDMDIN2)100 6 - GPIX is configured as a PDM data input for channel 5 and channel101 (PDMDIN3)102 7 - GPIX is configured as a PDM data input for channel 7 and channel103 (PDMDIN4)104 105 $ref: /schemas/types.yaml#/definitions/uint32-array106 minItems: 1107 maxItems: 4108 items:109 maximum: 7110 default: [0, 0, 0, 0]111 112 ti,gpio-config:113 description: |114 Defines the configuration and output drive for the General Purpose115 Input and Output pin (GPIO1). Its value is a pair, the first value is for116 the configuration type and the second value is for the output drive117 type. The array is defined as <GPIO1_CFG GPIO1_DRV>118 119 configuration for the GPIO pin can be one of the following:120 0 - disabled121 1 - GPIO1 is configured as a general-purpose output (GPO)122 2 - (default) GPIO1 is configured as a device interrupt output (IRQ)123 3 - GPIO1 is configured as a secondary ASI output (SDOUT2)124 4 - GPIO1 is configured as a PDM clock output (PDMCLK)125 8 - GPIO1 is configured as an input to control when MICBIAS turns on or126 off (MICBIAS_EN)127 9 - GPIO1 is configured as a general-purpose input (GPI)128 10 - GPIO1 is configured as a master clock input (MCLK)129 11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)130 12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2131 (PDMDIN1)132 13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4133 (PDMDIN2)134 14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6135 (PDMDIN3)136 15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8137 (PDMDIN4)138 139 output drive type for the GPIO pin can be one of the following:140 0 - Hi-Z output141 1 - Drive active low and active high142 2 - (default) Drive active low and weak high143 3 - Drive active low and Hi-Z144 4 - Drive weak low and active high145 5 - Drive Hi-Z and active high146 147 $ref: /schemas/types.yaml#/definitions/uint32-array148 minItems: 2149 maxItems: 2150 items:151 maximum: 15152 default: [2, 2]153 154 ti,asi-tx-drive:155 type: boolean156 description: |157 When set the device will set the Tx ASI output to a Hi-Z state for unused158 data cycles. Default is to drive the output low on unused ASI cycles.159 160patternProperties:161 '^ti,gpo-config-[1-4]$':162 $ref: /schemas/types.yaml#/definitions/uint32-array163 description: |164 Defines the configuration and output driver for the general purpose165 output pins (GPO). These values are pairs, the first value is for the166 configuration type and the second value is for the output drive type.167 The array is defined as <GPO_CFG GPO_DRV>168 169 GPO output configuration can be one of the following:170 171 0 - (default) disabled172 1 - GPOX is configured as a general-purpose output (GPO)173 2 - GPOX is configured as a device interrupt output (IRQ)174 3 - GPOX is configured as a secondary ASI output (SDOUT2)175 4 - GPOX is configured as a PDM clock output (PDMCLK)176 177 GPO output drive configuration for the GPO pins can be one of the following:178 179 0d - (default) Hi-Z output180 1d - Drive active low and active high181 2d - Drive active low and weak high182 3d - Drive active low and Hi-Z183 4d - Drive weak low and active high184 5d - Drive Hi-Z and active high185 186required:187 - compatible188 - reg189 190additionalProperties: false191 192examples:193 - |194 #include <dt-bindings/gpio/gpio.h>195 i2c {196 #address-cells = <1>;197 #size-cells = <0>;198 codec: codec@4c {199 compatible = "ti,tlv320adc5140";200 reg = <0x4c>;201 ti,mic-bias-source = <6>;202 ti,pdm-edge-select = <0 1 0 1>;203 ti,gpi-config = <4 5 6 7>;204 ti,gpio-config = <10 2>;205 ti,gpo-config-1 = <0 0>;206 ti,gpo-config-2 = <0 0>;207 reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;208 };209 };210