67 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Analog Devices AXI SPI Engine Controller8 9description: |10 The AXI SPI Engine controller is part of the SPI Engine framework[1] and11 allows memory mapped access to the SPI Engine control bus. This allows it12 to be used as a general purpose software driven SPI controller as well as13 some optional advanced acceleration and offloading capabilities.14 15 [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine16 17maintainers:18 - Michael Hennerich <Michael.Hennerich@analog.com>19 - Nuno Sá <nuno.sa@analog.com>20 21allOf:22 - $ref: /schemas/spi/spi-controller.yaml#23 24properties:25 compatible:26 const: adi,axi-spi-engine-1.00.a27 28 reg:29 maxItems: 130 31 interrupts:32 maxItems: 133 34 clocks:35 items:36 - description: The AXI interconnect clock.37 - description: The SPI controller clock.38 39 clock-names:40 items:41 - const: s_axi_aclk42 - const: spi_clk43 44required:45 - compatible46 - reg47 - interrupts48 - clocks49 - clock-names50 51unevaluatedProperties: false52 53examples:54 - |55 spi@44a00000 {56 compatible = "adi,axi-spi-engine-1.00.a";57 reg = <0x44a00000 0x1000>;58 interrupts = <0 56 4>;59 clocks = <&clkc 15>, <&clkc 15>;60 clock-names = "s_axi_aclk", "spi_clk";61 62 #address-cells = <1>;63 #size-cells = <0>;64 65 /* SPI devices */66 };67