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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries3%YAML 1.24---5$id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Atmel SPI device9 10maintainers:11 - Tudor Ambarus <tudor.ambarus@linaro.org>12 13allOf:14 - $ref: spi-controller.yaml#15 16properties:17 compatible:18 oneOf:19 - const: atmel,at91rm9200-spi20 - items:21 - enum:22 - microchip,sam9x60-spi23 - microchip,sam9x7-spi24 - microchip,sama7d65-spi25 - const: atmel,at91rm9200-spi26 27 reg:28 maxItems: 129 30 interrupts:31 maxItems: 132 33 clock-names:34 contains:35 const: spi_clk36 37 clocks:38 maxItems: 139 40 dmas:41 items:42 - description: TX DMA Channel43 - description: RX DMA Channel44 45 dma-names:46 items:47 - const: tx48 - const: rx49 50 atmel,fifo-size:51 $ref: /schemas/types.yaml#/definitions/uint3252 description: |53 Maximum number of data the RX and TX FIFOs can store for FIFO54 capable SPI controllers.55 enum: [ 16, 32 ]56 57required:58 - compatible59 - reg60 - interrupts61 - clock-names62 - clocks63 64unevaluatedProperties: false65 66examples:67 - |68 #include <dt-bindings/gpio/gpio.h>69 #include <dt-bindings/interrupt-controller/irq.h>70 71 spi1: spi@fffcc000 {72 compatible = "atmel,at91rm9200-spi";73 reg = <0xfffcc000 0x4000>;74 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;75 #address-cells = <1>;76 #size-cells = <0>;77 clocks = <&spi1_clk>;78 clock-names = "spi_clk";79 cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;80 atmel,fifo-size = <32>;81 82 mmc@0 {83 compatible = "mmc-spi-slot";84 reg = <0>;85 gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; /* CD */86 spi-max-frequency = <25000000>;87 };88 };89