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1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Broadcom Broadband SoC High Speed SPI controller8 9maintainers:10 - William Zhang <william.zhang@broadcom.com>11 - Kursad Oney <kursad.oney@broadcom.com>12 - Jonas Gorski <jonas.gorski@gmail.com>13 14description: |15 Broadcom Broadband SoC supports High Speed SPI master controller since the16 early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.017 controller was carried over to recent ARM based chips, such as BCM63138,18 BCM4908 and BCM6858. The old MIPS based chip should continue to use the19 brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to20 use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as21 defined below to match the specific chip along with ip revision info.22 23 This rev 1.0 controller has a limitation that can not keep the chip select line24 active between the SPI transfers within the same SPI message. This can25 terminate the transaction to some SPI devices prematurely. The issue can be26 worked around by either the controller's prepend mode or using the dummy chip27 select workaround. Driver automatically picks the suitable mode based on28 transfer type so it is transparent to the user.29 30 The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI31 controller rev 1.1 that add the capability to allow the driver to control chip32 select explicitly. This solves the issue in the old controller.33 34properties:35 compatible:36 oneOf:37 - const: brcm,bcm6328-hsspi38 - items:39 - enum:40 - brcm,bcm47622-hsspi41 - brcm,bcm4908-hsspi42 - brcm,bcm63138-hsspi43 - brcm,bcm63146-hsspi44 - brcm,bcm63148-hsspi45 - brcm,bcm63158-hsspi46 - brcm,bcm63178-hsspi47 - brcm,bcm6846-hsspi48 - brcm,bcm6856-hsspi49 - brcm,bcm6858-hsspi50 - brcm,bcm6878-hsspi51 - const: brcm,bcmbca-hsspi-v1.052 - items:53 - enum:54 - brcm,bcm4912-hsspi55 - brcm,bcm6756-hsspi56 - brcm,bcm6813-hsspi57 - brcm,bcm6855-hsspi58 - const: brcm,bcmbca-hsspi-v1.159 60 reg:61 items:62 - description: main registers63 - description: miscellaneous control registers64 minItems: 165 66 reg-names:67 items:68 - const: hsspi69 - const: spim-ctrl70 minItems: 171 72 clocks:73 items:74 - description: SPI master reference clock75 - description: SPI master pll clock76 77 clock-names:78 items:79 - const: hsspi80 - const: pll81 82 interrupts:83 maxItems: 184 85required:86 - compatible87 - reg88 - clocks89 - clock-names90 - interrupts91 92allOf:93 - $ref: spi-controller.yaml#94 - if:95 properties:96 compatible:97 contains:98 enum:99 - brcm,bcm6328-hsspi100 - brcm,bcmbca-hsspi-v1.0101 then:102 properties:103 reg:104 maxItems: 1105 reg-names:106 maxItems: 1107 else:108 properties:109 reg:110 minItems: 2111 maxItems: 2112 reg-names:113 minItems: 2114 maxItems: 2115 required:116 - reg-names117 118unevaluatedProperties: false119 120examples:121 - |122 #include <dt-bindings/interrupt-controller/arm-gic.h>123 spi@ff801000 {124 compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";125 reg = <0xff801000 0x1000>,126 <0xff802610 0x4>;127 reg-names = "hsspi", "spim-ctrl";128 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;129 clocks = <&hsspi>, <&hsspi_pll>;130 clock-names = "hsspi", "pll";131 num-cs = <8>;132 #address-cells = <1>;133 #size-cells = <0>;134 };135