102 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright 2020-21 Cadence3%YAML 1.24---5$id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Cadence XSPI Controller9 10maintainers:11 - Parshuram Thombare <pthombar@cadence.com>12 13description: |14 The XSPI controller allows SPI protocol communication in15 single, dual, quad or octal wire transmission modes for16 read/write access to slaves such as SPI-NOR flash.17 18properties:19 compatible:20 enum:21 - cdns,xspi-nor22 - marvell,cn10-xspi-nor23 24 reg:25 items:26 - description: address and length of the controller register set27 - description: address and length of the Slave DMA data port28 - description: address and length of the auxiliary registers29 - description: address and length of the xfer registers30 minItems: 331 32 reg-names:33 items:34 - const: io35 - const: sdma36 - const: aux37 - const: xfer38 minItems: 339 40 interrupts:41 maxItems: 142 43required:44 - compatible45 - reg46 - interrupts47 48allOf:49 - $ref: spi-controller.yaml#50 - if:51 properties:52 compatible:53 contains:54 enum:55 - marvell,cn10-xspi-nor56 then:57 properties:58 reg:59 minItems: 460 reg-names:61 minItems: 462 else:63 properties:64 reg:65 maxItems: 366 reg-names:67 maxItems: 368 69unevaluatedProperties: false70 71examples:72 - |73 #include <dt-bindings/interrupt-controller/irq.h>74 bus {75 #address-cells = <2>;76 #size-cells = <2>;77 78 xspi: spi@a0010000 {79 #address-cells = <1>;80 #size-cells = <0>;81 compatible = "cdns,xspi-nor";82 reg = <0x0 0xa0010000 0x0 0x1040>,83 <0x0 0xb0000000 0x0 0x1000>,84 <0x0 0xa0020000 0x0 0x100>;85 reg-names = "io", "sdma", "aux";86 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;87 interrupt-parent = <&gic>;88 89 flash@0 {90 compatible = "jedec,spi-nor";91 spi-max-frequency = <75000000>;92 reg = <0>;93 };94 95 flash@1 {96 compatible = "jedec,spi-nor";97 spi-max-frequency = <75000000>;98 reg = <1>;99 };100 };101 };102