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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Microchip FPGA {Q,}SPI Controllers8 9description:10 SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/11 fabric IP cores they are based on12 13maintainers:14 - Conor Dooley <conor.dooley@microchip.com>15 16properties:17 compatible:18 oneOf:19 - items:20 - enum:21 - microchip,mpfs-qspi22 - microchip,pic64gx-qspi23 - const: microchip,coreqspi-rtl-v224 - const: microchip,coreqspi-rtl-v2 # FPGA QSPI25 - items:26 - const: microchip,pic64gx-spi27 - const: microchip,mpfs-spi28 - const: microchip,mpfs-spi29 30 reg:31 maxItems: 132 33 interrupts:34 maxItems: 135 36 clock-names:37 maxItems: 138 39 clocks:40 maxItems: 141 42required:43 - compatible44 - reg45 - interrupts46 - clocks47 48allOf:49 - $ref: spi-controller.yaml#50 51 - if:52 properties:53 compatible:54 contains:55 const: microchip,mpfs-spi56 then:57 properties:58 num-cs:59 default: 160 61 - if:62 properties:63 compatible:64 contains:65 const: microchip,mpfs-spi66 not:67 required:68 - cs-gpios69 then:70 properties:71 num-cs:72 maximum: 173 74unevaluatedProperties: false75 76examples:77 - |78 #include "dt-bindings/clock/microchip,mpfs-clock.h"79 spi@20108000 {80 compatible = "microchip,mpfs-spi";81 reg = <0x20108000 0x1000>;82 clocks = <&clkcfg CLK_SPI0>;83 interrupt-parent = <&plic>;84 interrupts = <54>;85 };86...87