82 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/spi/nvidia,tegra20-sflash.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra20 SFLASH controller8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13properties:14 compatible:15 const: nvidia,tegra20-sflash16 17 reg:18 maxItems: 119 20 interrupts:21 maxItems: 122 23 clocks:24 items:25 - description: module clock26 27 resets:28 items:29 - description: module reset30 31 reset-names:32 items:33 - const: spi34 35 dmas:36 items:37 - description: DMA channel used for reception38 - description: DMA channel used for transmission39 40 dma-names:41 items:42 - const: rx43 - const: tx44 45 spi-max-frequency:46 description: Maximum SPI clocking speed of the controller in Hz.47 $ref: /schemas/types.yaml#/definitions/uint3248 49allOf:50 - $ref: spi-controller.yaml51 52unevaluatedProperties: false53 54required:55 - compatible56 - reg57 - interrupts58 - clocks59 - resets60 - reset-names61 - dmas62 - dma-names63 64examples:65 - |66 #include <dt-bindings/clock/tegra20-car.h>67 #include <dt-bindings/interrupt-controller/arm-gic.h>68 69 spi@7000c380 {70 compatible = "nvidia,tegra20-sflash";71 reg = <0x7000c380 0x80>;72 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;73 spi-max-frequency = <25000000>;74 #address-cells = <1>;75 #size-cells = <0>;76 clocks = <&tegra_car TEGRA20_CLK_SPI>;77 resets = <&tegra_car 43>;78 reset-names = "spi";79 dmas = <&apbdma 11>, <&apbdma 11>;80 dma-names = "rx", "tx";81 };82