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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Quad Serial Peripheral Interface (QSPI)8 9maintainers:10 - Bjorn Andersson <bjorn.andersson@linaro.org>11 12description: The QSPI controller allows SPI protocol communication in single,13 dual, or quad wire transmission modes for read/write access to slaves such14 as NOR flash.15 16allOf:17 - $ref: /schemas/spi/spi-controller.yaml#18 19properties:20 compatible:21 items:22 - enum:23 - qcom,sc7180-qspi24 - qcom,sc7280-qspi25 - qcom,sdm845-qspi26 27 - const: qcom,qspi-v128 29 reg:30 maxItems: 131 32 iommus:33 maxItems: 134 35 interrupts:36 maxItems: 137 38 clock-names:39 items:40 - const: iface41 - const: core42 43 clocks:44 items:45 - description: AHB clock46 - description: QSPI core clock47 48 interconnects:49 minItems: 150 maxItems: 251 52 interconnect-names:53 minItems: 154 items:55 - const: qspi-config56 - const: qspi-memory57 58 operating-points-v2: true59 60 power-domains:61 maxItems: 162 63required:64 - compatible65 - reg66 - interrupts67 - clock-names68 - clocks69 70unevaluatedProperties: false71 72examples:73 - |74 #include <dt-bindings/clock/qcom,gcc-sdm845.h>75 #include <dt-bindings/interrupt-controller/arm-gic.h>76 77 soc: soc {78 #address-cells = <2>;79 #size-cells = <2>;80 81 qspi: spi@88df000 {82 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";83 reg = <0 0x88df000 0 0x600>;84 #address-cells = <1>;85 #size-cells = <0>;86 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;87 clock-names = "iface", "core";88 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,89 <&gcc GCC_QSPI_CORE_CLK>;90 91 flash@0 {92 compatible = "jedec,spi-nor";93 reg = <0>;94 spi-max-frequency = <25000000>;95 spi-tx-bus-width = <2>;96 spi-rx-bus-width = <2>;97 };98 };99 };100...101