87 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/spi/spi-cadence.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cadence SPI controller8 9maintainers:10 - Michal Simek <michal.simek@amd.com>11 12allOf:13 - $ref: spi-controller.yaml#14 15properties:16 compatible:17 enum:18 - cdns,spi-r1p619 - xlnx,zynq-spi-r1p620 21 reg:22 maxItems: 123 24 interrupts:25 maxItems: 126 27 clock-names:28 items:29 - const: ref_clk30 - const: pclk31 32 clocks:33 maxItems: 234 35 num-cs:36 description: |37 Number of chip selects used. If a decoder is used,38 this will be the number of chip selects after the39 decoder.40 $ref: /schemas/types.yaml#/definitions/uint3241 minimum: 142 maximum: 443 default: 444 45 is-decoded-cs:46 description: |47 Flag to indicate whether decoder is used or not.48 $ref: /schemas/types.yaml#/definitions/uint3249 enum: [ 0, 1 ]50 default: 051 52 power-domains:53 maxItems: 154 55 label:56 description: Descriptive name of the SPI controller.57 58 resets:59 maxItems: 160 61 reset-names:62 items:63 - const: spi64 65required:66 - compatible67 - reg68 - interrupts69 - clock-names70 - clocks71 72unevaluatedProperties: false73 74examples:75 - |76 spi@e0007000 {77 compatible = "xlnx,zynq-spi-r1p6";78 clock-names = "ref_clk", "pclk";79 clocks = <&clkc 26>, <&clkc 35>;80 interrupt-parent = <&intc>;81 interrupts = <0 49 4>;82 num-cs = <4>;83 is-decoded-cs = <0>;84 reg = <0xe0007000 0x1000>;85 };86...87