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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/spi/spi-sifive.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: SiFive SPI controller8 9maintainers:10  - Pragnesh Patel <pragnesh.patel@sifive.com>11  - Paul Walmsley  <paul.walmsley@sifive.com>12  - Palmer Dabbelt <palmer@sifive.com>13 14allOf:15  - $ref: spi-controller.yaml#16 17properties:18  compatible:19    items:20      - enum:21          - sifive,fu540-c000-spi22          - sifive,fu740-c000-spi23      - const: sifive,spi024 25    description:26      Should be "sifive,<chip>-spi" and "sifive,spi<version>".27      Supported compatible strings are -28      "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v029      as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"30      for the SiFive SPI v0 IP block with no chip integration tweaks.31      Please refer to sifive-blocks-ip-versioning.txt for details32 33      SPI RTL that corresponds to the IP block version numbers can be found here -34      https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi35 36  reg:37    minItems: 138    items:39      - description: SPI registers region40      - description: Memory mapped flash region41 42  interrupts:43    maxItems: 144 45  clocks:46    maxItems: 147 48    description:49      Must reference the frequency given to the controller50 51  sifive,fifo-depth:52    description:53      Depth of hardware queues; defaults to 854    $ref: /schemas/types.yaml#/definitions/uint3255    enum: [8]56    default: 857 58  sifive,max-bits-per-word:59    description:60      Maximum bits per word; defaults to 861    $ref: /schemas/types.yaml#/definitions/uint3262    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]63    default: 864 65required:66  - compatible67  - reg68  - interrupts69  - clocks70 71unevaluatedProperties: false72 73examples:74  - |75    spi: spi@10040000 {76      compatible = "sifive,fu540-c000-spi", "sifive,spi0";77      reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;78      interrupt-parent = <&plic>;79      interrupts = <51>;80      clocks = <&tlclk>;81      #address-cells = <1>;82      #size-cells = <0>;83      sifive,fifo-depth = <8>;84      sifive,max-bits-per-word = <8>;85    };86 87...88