67 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller8 9maintainers:10 - Michal Simek <michal.simek@amd.com>11 12allOf:13 - $ref: spi-controller.yaml#14 15properties:16 compatible:17 enum:18 - xlnx,versal-qspi-1.019 - xlnx,zynqmp-qspi-1.020 21 reg:22 maxItems: 223 24 interrupts:25 maxItems: 126 27 clock-names:28 items:29 - const: ref_clk30 - const: pclk31 32 clocks:33 maxItems: 234 35 iommus:36 maxItems: 137 38 power-domains:39 maxItems: 140 41required:42 - compatible43 - reg44 - interrupts45 - clock-names46 - clocks47 48unevaluatedProperties: false49 50examples:51 - |52 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>53 soc {54 #address-cells = <2>;55 #size-cells = <2>;56 57 qspi: spi@ff0f0000 {58 compatible = "xlnx,zynqmp-qspi-1.0";59 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;60 clock-names = "ref_clk", "pclk";61 interrupts = <0 15 4>;62 interrupt-parent = <&gic>;63 reg = <0x0 0xff0f0000 0x0 0x1000>,64 <0x0 0xc0000000 0x0 0x8000000>;65 };66 };67