82 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Mediatek SPMI Controller8 9maintainers:10 - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>11 12description: |+13 On MediaTek SoCs the PMIC is connected via SPMI and the controller allows14 for multiple SoCs to control a single SPMI master.15 16allOf:17 - $ref: spmi.yaml18 19properties:20 compatible:21 oneOf:22 - enum:23 - mediatek,mt6873-spmi24 - mediatek,mt8195-spmi25 - items:26 - enum:27 - mediatek,mt8186-spmi28 - const: mediatek,mt8195-spmi29 30 reg:31 maxItems: 232 33 reg-names:34 items:35 - const: pmif36 - const: spmimst37 38 clocks:39 minItems: 340 maxItems: 341 42 clock-names:43 items:44 - const: pmif_sys_ck45 - const: pmif_tmr_ck46 - const: spmimst_clk_mux47 48 assigned-clocks:49 maxItems: 150 51 assigned-clock-parents:52 maxItems: 153 54required:55 - compatible56 - reg57 - reg-names58 - clocks59 - clock-names60 61unevaluatedProperties: false62 63examples:64 - |65 #include <dt-bindings/clock/mt8192-clk.h>66 67 spmi: spmi@10027000 {68 compatible = "mediatek,mt6873-spmi";69 reg = <0x10027000 0xe00>,70 <0x10029000 0x100>;71 reg-names = "pmif", "spmimst";72 clocks = <&infracfg CLK_INFRA_PMIC_AP>,73 <&infracfg CLK_INFRA_PMIC_TMR>,74 <&topckgen CLK_TOP_SPMI_MST_SEL>;75 clock-names = "pmif_sys_ck",76 "pmif_tmr_ck",77 "spmimst_clk_mux";78 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;79 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;80 };81...82