129 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SPMI Controller (PMIC Arbiter)8 9maintainers:10 - Stephen Boyd <sboyd@kernel.org>11 12description: |13 The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI14 controller with wrapping arbitration logic to allow for multiple on-chip15 devices to control a single SPMI master.16 17 The PMIC Arbiter can also act as an interrupt controller, providing interrupts18 to slave devices.19 20allOf:21 - $ref: spmi.yaml22 23properties:24 compatible:25 const: qcom,spmi-pmic-arb26 27 reg:28 oneOf:29 - items: # V130 - description: core registers31 - description: interrupt controller registers32 - description: configuration registers33 - items: # V234 - description: core registers35 - description: tx-channel per virtual slave regosters36 - description: rx-channel (called observer) per virtual slave registers37 - description: interrupt controller registers38 - description: configuration registers39 40 reg-names:41 oneOf:42 - items:43 - const: core44 - const: intr45 - const: cnfg46 - items:47 - const: core48 - const: chnls49 - const: obsrvr50 - const: intr51 - const: cnfg52 53 interrupts:54 maxItems: 155 56 interrupt-names:57 const: periph_irq58 59 interrupt-controller: true60 61 '#address-cells': true62 63 '#interrupt-cells':64 const: 465 description: |66 cell 1: slave ID for the requested interrupt (0-15)67 cell 2: peripheral ID for requested interrupt (0-255)68 cell 3: the requested peripheral interrupt (0-7)69 cell 4: interrupt flags indicating level-sense information,70 as defined in dt-bindings/interrupt-controller/irq.h71 72 '#size-cells': true73 74 qcom,ee:75 $ref: /schemas/types.yaml#/definitions/uint3276 minimum: 077 maximum: 578 description: >79 indicates the active Execution Environment identifier80 81 qcom,channel:82 $ref: /schemas/types.yaml#/definitions/uint3283 minimum: 084 maximum: 585 description: >86 which of the PMIC Arb provided channels to use for accesses87 88 qcom,bus-id:89 $ref: /schemas/types.yaml#/definitions/uint3290 minimum: 091 maximum: 192 description: >93 SPMI bus instance. only applicable to PMIC arbiter version 7 and beyond.94 Supported values, 0 = primary bus, 1 = secondary bus95 deprecated: true96 97required:98 - compatible99 - reg-names100 - qcom,ee101 - qcom,channel102 103unevaluatedProperties: false104 105examples:106 - |107 spmi@fc4cf000 {108 compatible = "qcom,spmi-pmic-arb";109 reg-names = "core", "intr", "cnfg";110 reg = <0xfc4cf000 0x1000>,111 <0xfc4cb000 0x1000>,112 <0xfc4ca000 0x1000>;113 114 interrupt-names = "periph_irq";115 interrupts = <0 190 0>;116 117 qcom,ee = <0>;118 qcom,channel = <0>;119 120 #address-cells = <2>;121 #size-cells = <0>;122 123 interrupt-controller;124 #interrupt-cells = <4>;125 126 qcom,bus-id = <0>;127 };128 129