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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7)8 9maintainers:10 - Stephen Boyd <sboyd@kernel.org>11 12description: |13 The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI14 controller with wrapping arbitration logic to allow for multiple on-chip15 devices to control up to 2 SPMI separate buses.16 17 The PMIC Arbiter can also act as an interrupt controller, providing interrupts18 to slave devices.19 20properties:21 compatible:22 const: qcom,x1e80100-spmi-pmic-arb23 24 reg:25 items:26 - description: core registers27 - description: tx-channel per virtual slave registers28 - description: rx-channel (called observer) per virtual slave registers29 30 reg-names:31 items:32 - const: core33 - const: chnls34 - const: obsrvr35 36 ranges: true37 38 '#address-cells':39 const: 240 41 '#size-cells':42 const: 243 44 qcom,ee:45 $ref: /schemas/types.yaml#/definitions/uint3246 minimum: 047 maximum: 548 description: >49 indicates the active Execution Environment identifier50 51 qcom,channel:52 $ref: /schemas/types.yaml#/definitions/uint3253 minimum: 054 maximum: 555 description: >56 which of the PMIC Arb provided channels to use for accesses57 58patternProperties:59 "^spmi@[a-f0-9]+$":60 type: object61 $ref: /schemas/spmi/spmi.yaml62 unevaluatedProperties: false63 64 properties:65 reg:66 items:67 - description: configuration registers68 - description: interrupt controller registers69 70 reg-names:71 items:72 - const: cnfg73 - const: intr74 75 interrupts:76 maxItems: 177 78 interrupt-names:79 const: periph_irq80 81 interrupt-controller: true82 83 '#interrupt-cells':84 const: 485 description: |86 cell 1: slave ID for the requested interrupt (0-15)87 cell 2: peripheral ID for requested interrupt (0-255)88 cell 3: the requested peripheral interrupt (0-7)89 cell 4: interrupt flags indicating level-sense information,90 as defined in dt-bindings/interrupt-controller/irq.h91 92required:93 - compatible94 - reg-names95 - qcom,ee96 - qcom,channel97 98additionalProperties: false99 100examples:101 - |102 #include <dt-bindings/interrupt-controller/arm-gic.h>103 104 soc {105 #address-cells = <2>;106 #size-cells = <2>;107 108 spmi: arbiter@c400000 {109 compatible = "qcom,x1e80100-spmi-pmic-arb";110 reg = <0 0x0c400000 0 0x3000>,111 <0 0x0c500000 0 0x4000000>,112 <0 0x0c440000 0 0x80000>;113 reg-names = "core", "chnls", "obsrvr";114 115 qcom,ee = <0>;116 qcom,channel = <0>;117 118 #address-cells = <2>;119 #size-cells = <2>;120 ranges;121 122 spmi_bus0: spmi@c42d000 {123 reg = <0 0x0c42d000 0 0x4000>,124 <0 0x0c4c0000 0 0x10000>;125 reg-names = "cnfg", "intr";126 127 interrupt-names = "periph_irq";128 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;129 interrupt-controller;130 #interrupt-cells = <4>;131 132 #address-cells = <2>;133 #size-cells = <0>;134 };135 };136 };137