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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ARM architected timer8 9maintainers:10 - Marc Zyngier <marc.zyngier@arm.com>11 - Mark Rutland <mark.rutland@arm.com>12description: |+13 ARM cores may have a per-core architected timer, which provides per-cpu timers,14 or a memory mapped architected timer, which provides up to 8 frames with a15 physical and optional virtual timer per frame.16 17 The per-core architected timer is attached to a GIC to deliver its18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC19 to deliver its interrupts via SPIs.20 21properties:22 compatible:23 oneOf:24 - items:25 - const: arm,cortex-a15-timer26 - const: arm,armv7-timer27 - items:28 - enum:29 - arm,armv7-timer30 - arm,armv8-timer31 - items:32 - const: arm,armv8-timer33 - const: arm,armv7-timer34 35 interrupts:36 minItems: 137 items:38 - description: secure timer irq39 - description: non-secure timer irq40 - description: virtual timer irq41 - description: hypervisor timer irq42 - description: hypervisor virtual timer irq43 44 interrupt-names:45 oneOf:46 - minItems: 247 items:48 - const: phys49 - const: virt50 - const: hyp-phys51 - const: hyp-virt52 - minItems: 353 items:54 - const: sec-phys55 - const: phys56 - const: virt57 - const: hyp-phys58 - const: hyp-virt59 60 clock-frequency:61 description: The frequency of the main counter, in Hz. Should be present62 only where necessary to work around broken firmware which does not configure63 CNTFRQ on all CPUs to a uniform correct value. Use of this property is64 strongly discouraged; fix your firmware unless absolutely impossible.65 66 always-on:67 type: boolean68 description: If present, the timer is powered through an always-on power69 domain, therefore it never loses context.70 71 allwinner,erratum-unknown1:72 type: boolean73 description: Indicates the presence of an erratum found in Allwinner SoCs,74 where reading certain values from the counter is unreliable. This also75 affects writes to the tval register, due to the implicit counter read.76 77 fsl,erratum-a008585:78 type: boolean79 description: Indicates the presence of QorIQ erratum A-008585, which says80 that reading the counter is unreliable unless the same value is returned81 by back-to-back reads. This also affects writes to the tval register, due82 to the implicit counter read.83 84 hisilicon,erratum-161010101:85 type: boolean86 description: Indicates the presence of Hisilicon erratum 161010101, which87 says that reading the counters is unreliable in some cases, and reads may88 return a value 32 beyond the correct value. This also affects writes to89 the tval registers, due to the implicit counter read.90 91 arm,cpu-registers-not-fw-configured:92 type: boolean93 description: Firmware does not initialize any of the generic timer CPU94 registers, which contain their architecturally-defined reset values. Only95 supported for 32-bit systems which follow the ARMv7 architected reset96 values.97 98 arm,no-tick-in-suspend:99 type: boolean100 description: The main counter does not tick when the system is in101 low-power system suspend on some SoCs. This behavior does not match the102 Architecture Reference Manual's specification that the system counter "must103 be implemented in an always-on power domain."104 105required:106 - compatible107 108additionalProperties: false109 110oneOf:111 - required:112 - interrupts113 - required:114 - interrupts-extended115 116examples:117 - |118 timer {119 compatible = "arm,cortex-a15-timer",120 "arm,armv7-timer";121 interrupts = <1 13 0xf08>,122 <1 14 0xf08>,123 <1 11 0xf08>,124 <1 10 0xf08>;125 clock-frequency = <100000000>;126 };127 128...129