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1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra timer8 9maintainers:10 - Stephen Warren <swarren@nvidia.com>11 12allOf:13 - if:14 properties:15 compatible:16 contains:17 const: nvidia,tegra210-timer18 then:19 properties:20 interrupts:21 # Either a single combined interrupt or up to 14 individual interrupts22 minItems: 123 maxItems: 1424 description: >25 A list of 14 interrupts; one per each timer channels 0 through 1326 27 - if:28 properties:29 compatible:30 oneOf:31 - items:32 - enum:33 - nvidia,tegra114-timer34 - nvidia,tegra124-timer35 - nvidia,tegra132-timer36 - const: nvidia,tegra30-timer37 - items:38 - const: nvidia,tegra30-timer39 - const: nvidia,tegra20-timer40 then:41 properties:42 interrupts:43 # Either a single combined interrupt or up to 6 individual interrupts44 minItems: 145 maxItems: 646 description: >47 A list of 6 interrupts; one per each of timer channels 1 through 5,48 and one for the shared interrupt for the remaining channels.49 50 - if:51 properties:52 compatible:53 const: nvidia,tegra20-timer54 then:55 properties:56 interrupts:57 # Either a single combined interrupt or up to 4 individual interrupts58 minItems: 159 maxItems: 460 description: |61 A list of 4 interrupts; one per timer channel.62 63properties:64 compatible:65 oneOf:66 - const: nvidia,tegra210-timer67 description: >68 The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit69 timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived70 from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock71 (TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,72 or watchdog interrupts.73 - items:74 - enum:75 - nvidia,tegra114-timer76 - nvidia,tegra124-timer77 - nvidia,tegra132-timer78 - const: nvidia,tegra30-timer79 - items:80 - const: nvidia,tegra30-timer81 - const: nvidia,tegra20-timer82 description: >83 The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free84 running counter, and 5 watchdog modules. The first two channels may also85 trigger a legacy watchdog reset.86 - const: nvidia,tegra20-timer87 description: >88 The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free89 running counter. The first two channels may also trigger a watchdog reset.90 91 reg:92 maxItems: 193 94 interrupts: true95 96 clocks:97 maxItems: 198 99 clock-names:100 items:101 - const: timer102 103 104required:105 - compatible106 - reg107 - interrupts108 - clocks109 110additionalProperties: false111 112examples:113 - |114 #include <dt-bindings/interrupt-controller/irq.h>115 timer@60005000 {116 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";117 reg = <0x60005000 0x400>;118 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,119 <0 1 IRQ_TYPE_LEVEL_HIGH>,120 <0 41 IRQ_TYPE_LEVEL_HIGH>,121 <0 42 IRQ_TYPE_LEVEL_HIGH>,122 <0 121 IRQ_TYPE_LEVEL_HIGH>,123 <0 122 IRQ_TYPE_LEVEL_HIGH>;124 clocks = <&tegra_car 214>;125 };126 - |127 #include <dt-bindings/clock/tegra210-car.h>128 #include <dt-bindings/interrupt-controller/arm-gic.h>129 #include <dt-bindings/interrupt-controller/irq.h>130 131 timer@60005000 {132 compatible = "nvidia,tegra210-timer";133 reg = <0x60005000 0x400>;134 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,135 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,137 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,138 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,139 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,140 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,141 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,142 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,143 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,144 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,145 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,146 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,147 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;148 clocks = <&tegra_car TEGRA210_CLK_TIMER>;149 clock-names = "timer";150 };151