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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra186 timer8 9maintainers:10 - Thierry Reding <treding@nvidia.com>11 12description: >13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp14 counter. Each NV timer selects its timing reference signal from the 1 MHz15 reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be16 programmed to generate one-shot, periodic, or watchdog interrupts.17 18 19properties:20 compatible:21 oneOf:22 - const: nvidia,tegra186-timer23 description: >24 The Tegra186 timer provides ten 29-bit timer counters.25 - const: nvidia,tegra234-timer26 description: >27 The Tegra234 timer provides sixteen 29-bit timer counters.28 29 reg:30 maxItems: 131 32 interrupts: true33 34allOf:35 - if:36 properties:37 compatible:38 contains:39 const: nvidia,tegra186-timer40 then:41 properties:42 interrupts:43 maxItems: 1044 description: >45 One per each timer channels 0 through 9.46 47 - if:48 properties:49 compatible:50 contains:51 const: nvidia,tegra234-timer52 then:53 properties:54 interrupts:55 maxItems: 1656 description: >57 One per each timer channels 0 through 15.58 59required:60 - compatible61 - reg62 - interrupts63 64additionalProperties: false65 66examples:67 - |68 #include <dt-bindings/interrupt-controller/arm-gic.h>69 #include <dt-bindings/interrupt-controller/irq.h>70 71 timer@3010000 {72 compatible = "nvidia,tegra186-timer";73 reg = <0x03010000 0x000e0000>;74 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,75 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,76 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,77 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,78 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,79 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,80 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,81 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,82 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,83 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;84 };85 86 - |87 #include <dt-bindings/interrupt-controller/arm-gic.h>88 #include <dt-bindings/interrupt-controller/irq.h>89 90 timer@2080000 {91 compatible = "nvidia,tegra234-timer";92 reg = <0x02080000 0x00121000>;93 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,94 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,95 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,96 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,97 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,98 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,99 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,100 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,101 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,102 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,103 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,104 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,105 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,106 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,107 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,108 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;109 };110