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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)8 9maintainers:10 - Biju Das <biju.das.jz@bp.renesas.com>11 12description: |13 This hardware block consists of eight 16-bit timer channels and one14 32-bit timer channel. It supports the following specifications:15 - Pulse input/output: 28 lines max16 - Pulse input 3 lines17 - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks18 for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination19 (when LWA = 1))20 - Operating frequency Up to 100 MHz21 - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]22 - Waveform output on compare match23 - Input capture function (noise filter setting available)24 - Counter-clearing operation25 - Simultaneous writing to multiple timer counters (TCNT)26 (excluding MTU8)27 - Simultaneous clearing on compare match or input capture28 (excluding MTU8)29 - Simultaneous input and output to registers in synchronization with30 counter operations (excluding MTU8)31 - Up to 12-phase PWM output in combination with synchronous operation32 (excluding MTU8)33 - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]34 - Buffer operation specifiable35 - [MTU1, MTU2]36 - Phase counting mode can be specified independently37 - 32-bit phase counting mode can be specified for interlocked operation38 of MTU1 and MTU2 (when TMDR3.LWA = 1)39 - Cascade connection operation available40 - [MTU3, MTU4, MTU6, and MTU7]41 - Through interlocked operation of MTU3/4 and MTU6/7, the positive and42 negative signals in six phases (12 phases in total) can be output in43 complementary PWM and reset-synchronized PWM operation44 - In complementary PWM mode, values can be transferred from buffer45 registers to temporary registers at crests and troughs of the timer-46 counter values or when the buffer registers (TGRD registers in MTU447 and MTU7) are written to48 - Double-buffering selectable in complementary PWM mode49 - [MTU3 and MTU4]50 - Through interlocking with MTU0, a mode for driving AC synchronous51 motors (brushless DC motors) by using complementary PWM output and52 reset-synchronized PWM output is settable and allows the selection53 of two types of waveform output (chopping or level)54 - [MTU5]55 - Capable of operation as a dead-time compensation counter56 - [MTU0/MTU5, MTU1, MTU2, and MTU8]57 - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and58 through interlocked operation with MTU0/MTU5 and MTU859 - Interrupt-skipping function60 - In complementary PWM mode, interrupts on crests and troughs of counter61 values and triggers to start conversion by the A/D converter can be62 skipped63 - Interrupt sources: 43 sources.64 - Buffer operation:65 - Automatic transfer of register data (transfer from the buffer66 register to the timer register).67 - Trigger generation68 - A/D converter start triggers can be generated69 - A/D converter start request delaying function enables A/D converter70 to be started with any desired timing and to be synchronized with71 PWM output72 - Low power consumption function73 - The MTU3a can be placed in the module-stop state74 75 There are two phase counting modes. 16-bit phase counting mode in which76 MTU1 and MTU2 operate independently, and cascade connection 32-bit phase77 counting mode in which MTU1 and MTU2 are cascaded.78 79 In phase counting mode, the phase difference between two external input80 clocks is detected and the corresponding TCNT is incremented or81 decremented.82 The below counters are supported83 count0 - MTU1 16-bit phase counting84 count1 - MTU2 16-bit phase counting85 count2 - MTU1+ MTU2 32-bit phase counting86 87 The module supports PWM mode{1,2}, Reset-synchronized PWM mode and88 complementary PWM mode{1,2,3}.89 90 In complementary PWM mode, six positive-phase and six negative-phase PWM91 waveforms (12 phases in total) with dead time can be output by92 combining MTU{3,4} and MTU{6,7}.93 94 The below pwm channels are supported in pwm mode 1.95 pwm0 - MTU0.MTIOC0A PWM mode 196 pwm1 - MTU0.MTIOC0C PWM mode 197 pwm2 - MTU1.MTIOC1A PWM mode 198 pwm3 - MTU2.MTIOC2A PWM mode 199 pwm4 - MTU3.MTIOC3A PWM mode 1100 pwm5 - MTU3.MTIOC3C PWM mode 1101 pwm6 - MTU4.MTIOC4A PWM mode 1102 pwm7 - MTU4.MTIOC4C PWM mode 1103 pwm8 - MTU6.MTIOC6A PWM mode 1104 pwm9 - MTU6.MTIOC6C PWM mode 1105 pwm10 - MTU7.MTIOC7A PWM mode 1106 pwm11 - MTU7.MTIOC7C PWM mode 1107 108properties:109 compatible:110 items:111 - enum:112 - renesas,r9a07g043-mtu3 # RZ/{G2UL,Five}113 - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}114 - renesas,r9a07g054-mtu3 # RZ/V2L115 - const: renesas,rz-mtu3116 117 reg:118 maxItems: 1119 120 interrupts:121 items:122 - description: MTU0.TGRA input capture/compare match123 - description: MTU0.TGRB input capture/compare match124 - description: MTU0.TGRC input capture/compare match125 - description: MTU0.TGRD input capture/compare match126 - description: MTU0.TCNT overflow127 - description: MTU0.TGRE compare match128 - description: MTU0.TGRF compare match129 - description: MTU1.TGRA input capture/compare match130 - description: MTU1.TGRB input capture/compare match131 - description: MTU1.TCNT overflow132 - description: MTU1.TCNT underflow133 - description: MTU2.TGRA input capture/compare match134 - description: MTU2.TGRB input capture/compare match135 - description: MTU2.TCNT overflow136 - description: MTU2.TCNT underflow137 - description: MTU3.TGRA input capture/compare match138 - description: MTU3.TGRB input capture/compare match139 - description: MTU3.TGRC input capture/compare match140 - description: MTU3.TGRD input capture/compare match141 - description: MTU3.TCNT overflow142 - description: MTU4.TGRA input capture/compare match143 - description: MTU4.TGRB input capture/compare match144 - description: MTU4.TGRC input capture/compare match145 - description: MTU4.TGRD input capture/compare match146 - description: MTU4.TCNT overflow/underflow147 - description: MTU5.TGRU input capture/compare match148 - description: MTU5.TGRV input capture/compare match149 - description: MTU5.TGRW input capture/compare match150 - description: MTU6.TGRA input capture/compare match151 - description: MTU6.TGRB input capture/compare match152 - description: MTU6.TGRC input capture/compare match153 - description: MTU6.TGRD input capture/compare match154 - description: MTU6.TCNT overflow155 - description: MTU7.TGRA input capture/compare match156 - description: MTU7.TGRB input capture/compare match157 - description: MTU7.TGRC input capture/compare match158 - description: MTU7.TGRD input capture/compare match159 - description: MTU7.TCNT overflow/underflow160 - description: MTU8.TGRA input capture/compare match161 - description: MTU8.TGRB input capture/compare match162 - description: MTU8.TGRC input capture/compare match163 - description: MTU8.TGRD input capture/compare match164 - description: MTU8.TCNT overflow165 - description: MTU8.TCNT underflow166 167 interrupt-names:168 items:169 - const: tgia0170 - const: tgib0171 - const: tgic0172 - const: tgid0173 - const: tciv0174 - const: tgie0175 - const: tgif0176 - const: tgia1177 - const: tgib1178 - const: tciv1179 - const: tciu1180 - const: tgia2181 - const: tgib2182 - const: tciv2183 - const: tciu2184 - const: tgia3185 - const: tgib3186 - const: tgic3187 - const: tgid3188 - const: tciv3189 - const: tgia4190 - const: tgib4191 - const: tgic4192 - const: tgid4193 - const: tciv4194 - const: tgiu5195 - const: tgiv5196 - const: tgiw5197 - const: tgia6198 - const: tgib6199 - const: tgic6200 - const: tgid6201 - const: tciv6202 - const: tgia7203 - const: tgib7204 - const: tgic7205 - const: tgid7206 - const: tciv7207 - const: tgia8208 - const: tgib8209 - const: tgic8210 - const: tgid8211 - const: tciv8212 - const: tciu8213 214 clocks:215 maxItems: 1216 217 power-domains:218 maxItems: 1219 220 resets:221 maxItems: 1222 223 "#pwm-cells":224 const: 2225 226required:227 - compatible228 - reg229 - interrupts230 - interrupt-names231 - clocks232 - power-domains233 - resets234 235additionalProperties: false236 237examples:238 - |239 #include <dt-bindings/clock/r9a07g044-cpg.h>240 #include <dt-bindings/interrupt-controller/arm-gic.h>241 242 mtu3: timer@10001200 {243 compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";244 reg = <0x10001200 0xb00>;245 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,246 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,247 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,248 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,249 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,250 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,251 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,252 <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,253 <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,254 <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,255 <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,256 <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,257 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,258 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,259 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,260 <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,261 <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,262 <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,263 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,264 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,265 <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,266 <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,267 <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,268 <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,269 <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,270 <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,271 <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,272 <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,273 <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,274 <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,275 <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,276 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,277 <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,278 <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,279 <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,280 <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,281 <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,282 <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,283 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,284 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,285 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,286 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,287 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,288 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;289 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0",290 "tgif0",291 "tgia1", "tgib1", "tciv1", "tciu1",292 "tgia2", "tgib2", "tciv2", "tciu2",293 "tgia3", "tgib3", "tgic3", "tgid3", "tciv3",294 "tgia4", "tgib4", "tgic4", "tgid4", "tciv4",295 "tgiu5", "tgiv5", "tgiw5",296 "tgia6", "tgib6", "tgic6", "tgid6", "tciv6",297 "tgia7", "tgib7", "tgic7", "tgid7", "tciv7",298 "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8";299 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;300 power-domains = <&cpg>;301 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;302 #pwm-cells = <2>;303 };304