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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: RISC-V timer8 9maintainers:10 - Anup Patel <anup@brainfault.org>11 12description: |+13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode14 based on the time CSR defined by the RISC-V privileged specification. The15 timer interrupts of this device are configured using the RISC-V SBI Time16 extension or the RISC-V Sstc extension.17 18 The clock frequency of RISC-V timer device is specified via the19 "timebase-frequency" DT property of "/cpus" DT node which is described20 in Documentation/devicetree/bindings/riscv/cpus.yaml21 22properties:23 compatible:24 enum:25 - riscv,timer26 27 interrupts-extended:28 minItems: 129 maxItems: 4096 # Should be enough?30 31 riscv,timer-cannot-wake-cpu:32 type: boolean33 description:34 If present, the timer interrupt cannot wake up the CPU from one or35 more suspend/idle states.36 37additionalProperties: false38 39required:40 - compatible41 - interrupts-extended42 43examples:44 - |45 timer {46 compatible = "riscv,timer";47 interrupts-extended = <&cpu1intc 5>,48 <&cpu2intc 5>,49 <&cpu3intc 5>,50 <&cpu4intc 5>;51 };52...53