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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: SiFive Core Local Interruptor8 9maintainers:10 - Palmer Dabbelt <palmer@dabbelt.com>11 - Anup Patel <anup.patel@wdc.com>12 13description:14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor16 interrupts. It directly connects to the timer and inter-processor interrupt17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local18 interrupt controller is the parent interrupt controller for CLINT device.19 The clock frequency of CLINT is specified via "timebase-frequency" DT20 property of "/cpus" DT node. The "timebase-frequency" DT property is21 described in Documentation/devicetree/bindings/riscv/cpus.yaml22 23 T-Head C906/C910 CPU cores include an implementation of CLINT too, however24 their implementation lacks a memory-mapped MTIME register, thus not25 compatible with SiFive ones.26 27properties:28 compatible:29 oneOf:30 - items:31 - enum:32 - canaan,k210-clint # Canaan Kendryte K21033 - sifive,fu540-c000-clint # SiFive FU54034 - starfive,jh7100-clint # StarFive JH710035 - starfive,jh7110-clint # StarFive JH711036 - starfive,jh8100-clint # StarFive JH810037 - const: sifive,clint0 # SiFive CLINT v0 IP block38 - items:39 - enum:40 - allwinner,sun20i-d1-clint41 - sophgo,cv1800b-clint42 - sophgo,cv1812h-clint43 - sophgo,sg2002-clint44 - thead,th1520-clint45 - const: thead,c900-clint46 - items:47 - const: sifive,clint048 - const: riscv,clint049 deprecated: true50 description: For the QEMU virt machine only51 52 description:53 Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"54 when compatible with a SiFive CLINT. Please refer to55 sifive-blocks-ip-versioning.txt for details regarding the latter.56 57 reg:58 maxItems: 159 60 interrupts-extended:61 minItems: 162 maxItems: 409563 64additionalProperties: false65 66required:67 - compatible68 - reg69 - interrupts-extended70 71examples:72 - |73 timer@2000000 {74 compatible = "sifive,fu540-c000-clint", "sifive,clint0";75 interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,76 <&cpu2intc 3>, <&cpu2intc 7>,77 <&cpu3intc 3>, <&cpu3intc 7>,78 <&cpu4intc 3>, <&cpu4intc 7>;79 reg = <0x2000000 0x10000>;80 };81...82