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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Tegra on chip generic hardware timestamping engine (HTE) provider8 9maintainers:10 - Dipen Patel <dipenp@nvidia.com>11 12description:13 Tegra SoC has two instances of generic hardware timestamping engines (GTE)14 known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip15 IRQ lines for the state change respectively, upon detection it will record16 timestamp (taken from system counter) in its internal hardware FIFO. It has17 a bitmap array arranged in 32bit slices where each bit represent signal/line18 to enable or disable for the hardware timestamping. The GTE GPIO monitors19 GPIO lines from the AON (always on) GPIO controller.20 21properties:22 compatible:23 enum:24 - nvidia,tegra194-gte-aon25 - nvidia,tegra194-gte-lic26 - nvidia,tegra234-gte-aon27 - nvidia,tegra234-gte-lic28 29 reg:30 maxItems: 131 32 interrupts:33 maxItems: 134 35 nvidia,int-threshold:36 $ref: /schemas/types.yaml#/definitions/uint3237 description:38 HTE device generates its interrupt based on this u32 FIFO threshold39 value. The recommended value is 1.40 minimum: 141 maximum: 25642 43 nvidia,slices:44 $ref: /schemas/types.yaml#/definitions/uint3245 deprecated: true46 description:47 HTE lines are arranged in 32 bit slice where each bit represents different48 line/signal that it can enable/configure for the timestamp. It is u3249 property and the value depends on the HTE instance in the chip. The AON50 GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra19451 LIC instance has 11 slices and Tegra234 LIC has 17 slices.52 enum: [3, 11, 17]53 54 nvidia,gpio-controller:55 $ref: /schemas/types.yaml#/definitions/phandle56 description:57 The phandle to AON gpio controller instance. This is required to handle58 namespace conversion between GPIO and GTE.59 60 '#timestamp-cells':61 description:62 This represents number of line id arguments as specified by the63 consumers. For the GTE IRQ, this is IRQ number as mentioned in the64 SoC technical reference manual. For the GTE GPIO, its value is same as65 mentioned in the nvidia GPIO device tree binding document.66 const: 167 68required:69 - compatible70 - reg71 - interrupts72 - "#timestamp-cells"73 74allOf:75 - if:76 properties:77 compatible:78 contains:79 enum:80 - nvidia,tegra194-gte-aon81 - nvidia,tegra234-gte-aon82 then:83 properties:84 nvidia,slices:85 const: 386 87 - if:88 properties:89 compatible:90 contains:91 enum:92 - nvidia,tegra194-gte-lic93 then:94 properties:95 nvidia,slices:96 const: 1197 98 - if:99 properties:100 compatible:101 contains:102 enum:103 - nvidia,tegra234-gte-lic104 then:105 properties:106 nvidia,slices:107 const: 17108 109 - if:110 properties:111 compatible:112 contains:113 enum:114 - nvidia,tegra234-gte-aon115 then:116 required:117 - nvidia,gpio-controller118 119additionalProperties: false120 121examples:122 - |123 tegra_hte_aon: timestamp@c1e0000 {124 compatible = "nvidia,tegra194-gte-aon";125 reg = <0xc1e0000 0x10000>;126 interrupts = <0 13 0x4>;127 nvidia,int-threshold = <1>;128 #timestamp-cells = <1>;129 };130 131 - |132 tegra_hte_lic: timestamp@3aa0000 {133 compatible = "nvidia,tegra194-gte-lic";134 reg = <0x3aa0000 0x10000>;135 interrupts = <0 11 0x4>;136 nvidia,int-threshold = <1>;137 #timestamp-cells = <1>;138 };139 140...141