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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/tpm/google,cr50.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Google Security Chip H1 (running Cr50 firmware)8 9maintainers:10 - Andrey Pronin <apronin@chromium.org>11 12description: |13 Google has designed a family of security chips called "Titan".14 One member is the H1 built into Chromebooks and running Cr50 firmware:15 https://www.osfc.io/2018/talks/google-secure-microcontroller-and-ccd-closed-case-debugging/16 17 The chip provides several functions, including TPM 2.0 like functionality.18 It communicates over SPI or I²C using the FIFO protocol described in the19 TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP), sec 6:20 https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/21 22properties:23 compatible:24 const: google,cr5025 26allOf:27 - $ref: tpm-common.yaml#28 29anyOf:30 - $ref: /schemas/spi/spi-peripheral-props.yaml#31 - $ref: tcg,tpm-tis-i2c.yaml#/properties/reg32 33required:34 - compatible35 - reg36 37unevaluatedProperties: false38 39examples:40 - |41 spi {42 #address-cells = <1>;43 #size-cells = <0>;44 45 tpm@0 {46 reg = <0>;47 compatible = "google,cr50";48 spi-max-frequency = <800000>;49 };50 };51 52 - |53 #include <dt-bindings/interrupt-controller/irq.h>54 i2c {55 #address-cells = <1>;56 #size-cells = <0>;57 58 tpm@50 {59 compatible = "google,cr50";60 reg = <0x50>;61 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;62 pinctrl-names = "default";63 pinctrl-0 = <&cr50_int>;64 };65 };66