74 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cadence Universal Flash Storage (UFS) Controller8 9maintainers:10 - Jan Kotas <jank@cadence.com>11 12# Select only our matches, not all jedec,ufs-2.013select:14 properties:15 compatible:16 contains:17 enum:18 - cdns,ufshc19 - cdns,ufshc-m31-16nm20 required:21 - compatible22 23allOf:24 - $ref: ufs-common.yaml25 26properties:27 compatible:28 items:29 - enum:30 - cdns,ufshc31 # CDNS UFS HC + M31 16nm PHY32 - cdns,ufshc-m31-16nm33 - const: jedec,ufs-2.034 35 clocks:36 minItems: 137 maxItems: 338 39 clock-names:40 minItems: 141 items:42 - const: core_clk43 - const: phy_clk44 - const: ref_clk45 46 power-domains:47 maxItems: 148 49 reg:50 maxItems: 151 52 dma-coherent: true53 54required:55 - compatible56 - clocks57 - clock-names58 - reg59 60unevaluatedProperties: false61 62examples:63 - |64 #include <dt-bindings/interrupt-controller/arm-gic.h>65 66 ufs@fd030000 {67 compatible = "cdns,ufshc", "jedec,ufs-2.0";68 reg = <0xfd030000 0x10000>;69 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;70 freq-table-hz = <0 0>, <0 0>;71 clocks = <&ufs_core_clk>, <&ufs_phy_clk>;72 clock-names = "core_clk", "phy_clk";73 };74