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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Universal Flash Storage (UFS) Controller8 9maintainers:10 - Bjorn Andersson <bjorn.andersson@linaro.org>11 - Andy Gross <agross@kernel.org>12 13# Select only our matches, not all jedec,ufs-2.014select:15 properties:16 compatible:17 contains:18 const: qcom,ufshc19 required:20 - compatible21 22properties:23 compatible:24 items:25 - enum:26 - qcom,msm8994-ufshc27 - qcom,msm8996-ufshc28 - qcom,msm8998-ufshc29 - qcom,sa8775p-ufshc30 - qcom,sc7180-ufshc31 - qcom,sc7280-ufshc32 - qcom,sc8180x-ufshc33 - qcom,sc8280xp-ufshc34 - qcom,sdm845-ufshc35 - qcom,sm6115-ufshc36 - qcom,sm6125-ufshc37 - qcom,sm6350-ufshc38 - qcom,sm8150-ufshc39 - qcom,sm8250-ufshc40 - qcom,sm8350-ufshc41 - qcom,sm8450-ufshc42 - qcom,sm8550-ufshc43 - qcom,sm8650-ufshc44 - const: qcom,ufshc45 - const: jedec,ufs-2.046 47 clocks:48 minItems: 749 maxItems: 950 51 clock-names:52 minItems: 753 maxItems: 954 55 dma-coherent: true56 57 interconnects:58 minItems: 259 maxItems: 260 61 interconnect-names:62 items:63 - const: ufs-ddr64 - const: cpu-ufs65 66 iommus:67 minItems: 168 maxItems: 269 70 phys:71 maxItems: 172 73 phy-names:74 items:75 - const: ufsphy76 77 power-domains:78 maxItems: 179 80 qcom,ice:81 $ref: /schemas/types.yaml#/definitions/phandle82 description: phandle to the Inline Crypto Engine node83 84 reg:85 minItems: 186 maxItems: 287 88 reg-names:89 items:90 - const: std91 - const: ice92 93 required-opps:94 maxItems: 195 96 resets:97 maxItems: 198 99 '#reset-cells':100 const: 1101 102 reset-names:103 items:104 - const: rst105 106 reset-gpios:107 maxItems: 1108 description:109 GPIO connected to the RESET pin of the UFS memory device.110 111required:112 - compatible113 - reg114 115allOf:116 - $ref: ufs-common.yaml117 118 - if:119 properties:120 compatible:121 contains:122 enum:123 - qcom,sc7180-ufshc124 then:125 properties:126 clocks:127 minItems: 7128 maxItems: 7129 clock-names:130 items:131 - const: core_clk132 - const: bus_aggr_clk133 - const: iface_clk134 - const: core_clk_unipro135 - const: ref_clk136 - const: tx_lane0_sync_clk137 - const: rx_lane0_sync_clk138 reg:139 maxItems: 1140 reg-names:141 maxItems: 1142 143 - if:144 properties:145 compatible:146 contains:147 enum:148 - qcom,msm8998-ufshc149 - qcom,sa8775p-ufshc150 - qcom,sc7280-ufshc151 - qcom,sc8180x-ufshc152 - qcom,sc8280xp-ufshc153 - qcom,sm8250-ufshc154 - qcom,sm8350-ufshc155 - qcom,sm8450-ufshc156 - qcom,sm8550-ufshc157 - qcom,sm8650-ufshc158 then:159 properties:160 clocks:161 minItems: 8162 maxItems: 8163 clock-names:164 items:165 - const: core_clk166 - const: bus_aggr_clk167 - const: iface_clk168 - const: core_clk_unipro169 - const: ref_clk170 - const: tx_lane0_sync_clk171 - const: rx_lane0_sync_clk172 - const: rx_lane1_sync_clk173 reg:174 minItems: 1175 maxItems: 1176 reg-names:177 maxItems: 1178 179 - if:180 properties:181 compatible:182 contains:183 enum:184 - qcom,sdm845-ufshc185 - qcom,sm6350-ufshc186 - qcom,sm8150-ufshc187 then:188 properties:189 clocks:190 minItems: 9191 maxItems: 9192 clock-names:193 items:194 - const: core_clk195 - const: bus_aggr_clk196 - const: iface_clk197 - const: core_clk_unipro198 - const: ref_clk199 - const: tx_lane0_sync_clk200 - const: rx_lane0_sync_clk201 - const: rx_lane1_sync_clk202 - const: ice_core_clk203 reg:204 minItems: 2205 maxItems: 2206 reg-names:207 minItems: 2208 required:209 - reg-names210 211 - if:212 properties:213 compatible:214 contains:215 enum:216 - qcom,msm8996-ufshc217 then:218 properties:219 clocks:220 minItems: 9221 maxItems: 9222 clock-names:223 items:224 - const: core_clk225 - const: bus_clk226 - const: bus_aggr_clk227 - const: iface_clk228 - const: core_clk_unipro229 - const: core_clk_ice230 - const: ref_clk231 - const: tx_lane0_sync_clk232 - const: rx_lane0_sync_clk233 reg:234 minItems: 1235 maxItems: 1236 reg-names:237 maxItems: 1238 239 - if:240 properties:241 compatible:242 contains:243 enum:244 - qcom,sm6115-ufshc245 - qcom,sm6125-ufshc246 then:247 properties:248 clocks:249 minItems: 8250 maxItems: 8251 clock-names:252 items:253 - const: core_clk254 - const: bus_aggr_clk255 - const: iface_clk256 - const: core_clk_unipro257 - const: ref_clk258 - const: tx_lane0_sync_clk259 - const: rx_lane0_sync_clk260 - const: ice_core_clk261 reg:262 minItems: 2263 maxItems: 2264 reg-names:265 minItems: 2266 required:267 - reg-names268 269 # TODO: define clock bindings for qcom,msm8994-ufshc270 271 - if:272 required:273 - qcom,ice274 then:275 properties:276 reg:277 maxItems: 1278 clocks:279 minItems: 7280 maxItems: 8281 else:282 properties:283 reg:284 minItems: 1285 maxItems: 2286 clocks:287 minItems: 7288 maxItems: 9289 290unevaluatedProperties: false291 292examples:293 - |294 #include <dt-bindings/clock/qcom,gcc-sm8450.h>295 #include <dt-bindings/clock/qcom,rpmh.h>296 #include <dt-bindings/gpio/gpio.h>297 #include <dt-bindings/interconnect/qcom,sm8450.h>298 #include <dt-bindings/interrupt-controller/arm-gic.h>299 300 soc {301 #address-cells = <2>;302 #size-cells = <2>;303 304 ufs@1d84000 {305 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",306 "jedec,ufs-2.0";307 reg = <0 0x01d84000 0 0x3000>;308 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;309 phys = <&ufs_mem_phy_lanes>;310 phy-names = "ufsphy";311 lanes-per-direction = <2>;312 #reset-cells = <1>;313 resets = <&gcc GCC_UFS_PHY_BCR>;314 reset-names = "rst";315 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;316 317 vcc-supply = <&vreg_l7b_2p5>;318 vcc-max-microamp = <1100000>;319 vccq-supply = <&vreg_l9b_1p2>;320 vccq-max-microamp = <1200000>;321 322 power-domains = <&gcc UFS_PHY_GDSC>;323 iommus = <&apps_smmu 0xe0 0x0>;324 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,325 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;326 interconnect-names = "ufs-ddr", "cpu-ufs";327 328 clock-names = "core_clk",329 "bus_aggr_clk",330 "iface_clk",331 "core_clk_unipro",332 "ref_clk",333 "tx_lane0_sync_clk",334 "rx_lane0_sync_clk",335 "rx_lane1_sync_clk";336 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,337 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,338 <&gcc GCC_UFS_PHY_AHB_CLK>,339 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,340 <&rpmhcc RPMH_CXO_CLK>,341 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,342 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,343 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;344 freq-table-hz = <75000000 300000000>,345 <0 0>,346 <0 0>,347 <75000000 300000000>,348 <75000000 300000000>,349 <0 0>,350 <0 0>,351 <0 0>;352 qcom,ice = <&ice>;353 };354 };355