131 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Samsung SoC series UFS host controller8 9maintainers:10 - Alim Akhtar <alim.akhtar@samsung.com>11 12description: |13 Each Samsung UFS host controller instance should have its own node.14 15properties:16 compatible:17 enum:18 - google,gs101-ufs19 - samsung,exynos7-ufs20 - samsung,exynosautov9-ufs21 - samsung,exynosautov9-ufs-vh22 - tesla,fsd-ufs23 24 reg:25 items:26 - description: HCI register27 - description: vendor specific register28 - description: unipro register29 - description: UFS protector register30 31 reg-names:32 items:33 - const: hci34 - const: vs_hci35 - const: unipro36 - const: ufsp37 38 clocks:39 minItems: 240 items:41 - description: ufs link core clock42 - description: unipro main clock43 - description: fmp clock44 - description: ufs aclk clock45 - description: ufs pclk clock46 - description: sysreg clock47 48 clock-names:49 minItems: 250 items:51 - const: core_clk52 - const: sclk_unipro_main53 - const: fmp54 - const: aclk55 - const: pclk56 - const: sysreg57 58 phys:59 maxItems: 160 61 phy-names:62 const: ufs-phy63 64 samsung,sysreg:65 $ref: /schemas/types.yaml#/definitions/phandle-array66 items:67 - items:68 - description: phandle to FSYSx sysreg node69 - description: offset of the control register for UFS io coherency setting70 description:71 Phandle and offset to the FSYSx sysreg for UFS io coherency setting.72 73 dma-coherent: true74 75required:76 - compatible77 - reg78 - phys79 - phy-names80 - clocks81 - clock-names82 83allOf:84 - $ref: ufs-common.yaml85 - if:86 properties:87 compatible:88 contains:89 const: google,gs101-ufs90 91 then:92 properties:93 clocks:94 minItems: 695 96 clock-names:97 minItems: 698 99 else:100 properties:101 clocks:102 maxItems: 2103 104 clock-names:105 maxItems: 2106 107unevaluatedProperties: false108 109examples:110 - |111 #include <dt-bindings/interrupt-controller/arm-gic.h>112 #include <dt-bindings/clock/exynos7-clk.h>113 114 ufs: ufs@15570000 {115 compatible = "samsung,exynos7-ufs";116 reg = <0x15570000 0x100>,117 <0x15570100 0x100>,118 <0x15571000 0x200>,119 <0x15572000 0x300>;120 reg-names = "hci", "vs_hci", "unipro", "ufsp";121 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;122 clocks = <&clock_fsys1 ACLK_UFS20_LINK>,123 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;124 clock-names = "core_clk", "sclk_unipro_main";125 pinctrl-names = "default";126 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;127 phys = <&ufs_phy>;128 phy-names = "ufs-phy";129 };130...131