137 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx SuperSpeed DWC3 USB SoC controller8 9maintainers:10 - Mubin Sayyed <mubin.sayyed@amd.com>11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>12 13properties:14 compatible:15 items:16 - enum:17 - xlnx,zynqmp-dwc318 - xlnx,versal-dwc319 reg:20 maxItems: 121 22 "#address-cells":23 enum: [ 1, 2 ]24 25 "#size-cells":26 enum: [ 1, 2 ]27 28 ranges: true29 30 power-domains:31 description: specifies a phandle to PM domain provider node32 maxItems: 133 34 clocks:35 description:36 A list of phandle and clock-specifier pairs for the clocks37 listed in clock-names.38 items:39 - description: Master/Core clock, has to be >= 125 MHz40 for SS operation and >= 60MHz for HS operation.41 - description: Clock source to core during PHY power down.42 43 clock-names:44 items:45 - const: bus_clk46 - const: ref_clk47 48 resets:49 description:50 A list of phandles for resets listed in reset-names.51 52 items:53 - description: USB core reset54 - description: USB hibernation reset55 - description: USB APB reset56 57 reset-names:58 items:59 - const: usb_crst60 - const: usb_hibrst61 - const: usb_apbrst62 63 phys:64 minItems: 165 maxItems: 266 67 phy-names:68 minItems: 169 maxItems: 270 items:71 enum:72 - usb2-phy73 - usb3-phy74 75 reset-gpios:76 description: GPIO used for the reset ulpi-phy77 maxItems: 178 79# Required child node:80 81patternProperties:82 "^usb@[0-9a-f]+$":83 $ref: snps,dwc3.yaml#84 85required:86 - compatible87 - reg88 - "#address-cells"89 - "#size-cells"90 - ranges91 - power-domains92 - clocks93 - clock-names94 - resets95 - reset-names96 97additionalProperties: false98 99examples:100 - |101 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>102 #include <dt-bindings/power/xlnx-zynqmp-power.h>103 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>104 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>105 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>106 #include <dt-bindings/phy/phy.h>107 axi {108 #address-cells = <2>;109 #size-cells = <2>;110 111 usb@0 {112 #address-cells = <0x2>;113 #size-cells = <0x2>;114 compatible = "xlnx,zynqmp-dwc3";115 reg = <0x0 0xff9d0000 0x0 0x100>;116 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;117 clock-names = "bus_clk", "ref_clk";118 power-domains = <&zynqmp_firmware PD_USB_0>;119 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,120 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,121 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;122 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";123 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;124 phy-names = "usb3-phy";125 ranges;126 127 usb@fe200000 {128 compatible = "snps,dwc3";129 reg = <0x0 0xfe200000 0x0 0x40000>;130 interrupt-names = "host", "otg";131 interrupts = <0 65 4>, <0 69 4>;132 dr_mode = "host";133 dma-coherent;134 };135 };136 };137