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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (c) 2020 NXP3%YAML 1.24---5$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: NXP iMX8MP Soc USB Controller9 10maintainers:11 - Li Jun <jun.li@nxp.com>12 13properties:14 compatible:15 const: fsl,imx8mp-dwc316 17 reg:18 items:19 - description: Address and length of the register set for HSIO Block Control20 - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.21 22 "#address-cells":23 enum: [ 1, 2 ]24 25 "#size-cells":26 enum: [ 1, 2 ]27 28 dma-ranges:29 description:30 See section 2.3.9 of the DeviceTree Specification.31 32 ranges: true33 34 interrupts:35 maxItems: 136 description: The interrupt that is asserted when a wakeup event is37 received.38 39 clocks:40 description:41 A list of phandle and clock-specifier pairs for the clocks42 listed in clock-names.43 items:44 - description: system hsio root clock.45 - description: suspend clock, used for usb wakeup logic.46 47 clock-names:48 items:49 - const: hsio50 - const: suspend51 52 fsl,permanently-attached:53 type: boolean54 description:55 Indicates if the device attached to a downstream port is56 permanently attached.57 58 fsl,disable-port-power-control:59 type: boolean60 description:61 Indicates whether the host controller implementation includes port62 power control. Defines Bit 3 in capability register (HCCPARAMS).63 64 fsl,over-current-active-low:65 type: boolean66 description:67 Over current signal polarity is active low.68 69 fsl,power-active-low:70 type: boolean71 description:72 Power pad (PWR) polarity is active low.73 74 power-domains:75 maxItems: 176 77# Required child node:78 79patternProperties:80 "^usb@[0-9a-f]+$":81 $ref: snps,dwc3.yaml#82 83required:84 - compatible85 - reg86 - "#address-cells"87 - "#size-cells"88 - dma-ranges89 - ranges90 - clocks91 - clock-names92 - interrupts93 - power-domains94 95additionalProperties: false96 97examples:98 - |99 #include <dt-bindings/clock/imx8mp-clock.h>100 #include <dt-bindings/power/imx8mp-power.h>101 #include <dt-bindings/interrupt-controller/arm-gic.h>102 usb3_0: usb@32f10100 {103 compatible = "fsl,imx8mp-dwc3";104 reg = <0x32f10100 0x8>,105 <0x381f0000 0x20>;106 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,107 <&clk IMX8MP_CLK_USB_ROOT>;108 clock-names = "hsio", "suspend";109 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;110 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;111 #address-cells = <1>;112 #size-cells = <1>;113 dma-ranges = <0x40000000 0x40000000 0xc0000000>;114 ranges;115 116 usb@38100000 {117 compatible = "snps,dwc3";118 reg = <0x38100000 0x10000>;119 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,120 <&clk IMX8MP_CLK_USB_CORE_REF>,121 <&clk IMX8MP_CLK_USB_ROOT>;122 clock-names = "bus_early", "ref", "suspend";123 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;124 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;125 assigned-clock-rates = <500000000>;126 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;127 phys = <&usb3_phy0>, <&usb3_phy0>;128 phy-names = "usb2-phy", "usb3-phy";129 snps,dis-u2-freeclk-exists-quirk;130 };131 };132