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1HiSilicon STB xHCI2 3The device node for HiSilicon STB xHCI host controller4 5Required properties:6 - compatible: should be "hisilicon,hi3798cv200-xhci"7 - reg: specifies physical base address and size of the registers8 - interrupts : interrupt used by the controller9 - clocks: a list of phandle + clock-specifier pairs, one for each10 entry in clock-names11 - clock-names: must contain12 "bus": for bus clock13 "utmi": for utmi clock14 "pipe": for pipe clock15 "suspend": for suspend clock16 - resets: a list of phandle and reset specifier pairs as listed in17 reset-names property.18 - reset-names: must contain19 "soft": for soft reset20 - phys: a list of phandle + phy specifier pairs21 - phy-names: must contain at least one of following:22 "inno": for inno phy23 "combo": for combo phy24 25Optional properties:26 - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM27 - usb3-lpm-capable: determines if platform is USB3 LPM capable28 - imod-interval-ns: default interrupt moderation interval is 40000ns29 30Example:31 32xhci0: xchi@f98a0000 {33 compatible = "hisilicon,hi3798cv200-xhci";34 reg = <0xf98a0000 0x10000>;35 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;36 clocks = <&crg HISTB_USB3_BUS_CLK>,37 <&crg HISTB_USB3_UTMI_CLK>,38 <&crg HISTB_USB3_PIPE_CLK>,39 <&crg HISTB_USB3_SUSPEND_CLK>;40 clock-names = "bus", "utmi", "pipe", "suspend";41 resets = <&crg 0xb0 12>;42 reset-names = "soft";43 phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>;44 phy-names = "inno", "combo";45};46