614 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller8 9maintainers:10 - Wesley Cheng <quic_wcheng@quicinc.com>11 12properties:13 compatible:14 items:15 - enum:16 - qcom,ipq4019-dwc317 - qcom,ipq5018-dwc318 - qcom,ipq5332-dwc319 - qcom,ipq6018-dwc320 - qcom,ipq8064-dwc321 - qcom,ipq8074-dwc322 - qcom,ipq9574-dwc323 - qcom,msm8953-dwc324 - qcom,msm8994-dwc325 - qcom,msm8996-dwc326 - qcom,msm8998-dwc327 - qcom,qcm2290-dwc328 - qcom,qcs404-dwc329 - qcom,qdu1000-dwc330 - qcom,sa8775p-dwc331 - qcom,sc7180-dwc332 - qcom,sc7280-dwc333 - qcom,sc8180x-dwc334 - qcom,sc8180x-dwc3-mp35 - qcom,sc8280xp-dwc336 - qcom,sc8280xp-dwc3-mp37 - qcom,sdm660-dwc338 - qcom,sdm670-dwc339 - qcom,sdm845-dwc340 - qcom,sdx55-dwc341 - qcom,sdx65-dwc342 - qcom,sdx75-dwc343 - qcom,sm4250-dwc344 - qcom,sm6115-dwc345 - qcom,sm6125-dwc346 - qcom,sm6350-dwc347 - qcom,sm6375-dwc348 - qcom,sm8150-dwc349 - qcom,sm8250-dwc350 - qcom,sm8350-dwc351 - qcom,sm8450-dwc352 - qcom,sm8550-dwc353 - qcom,sm8650-dwc354 - qcom,x1e80100-dwc355 - qcom,x1e80100-dwc3-mp56 - const: qcom,dwc357 58 reg:59 description: Offset and length of register set for QSCRATCH wrapper60 maxItems: 161 62 "#address-cells":63 enum: [ 1, 2 ]64 65 "#size-cells":66 enum: [ 1, 2 ]67 68 ranges: true69 70 power-domains:71 description: specifies a phandle to PM domain provider node72 maxItems: 173 74 required-opps:75 maxItems: 176 77 clocks:78 description: |79 Several clocks are used, depending on the variant. Typical ones are::80 - cfg_noc:: System Config NOC clock.81 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=82 60MHz for HS operation.83 - iface:: System bus AXI clock.84 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low85 power mode (U3).86 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host87 mode. Its frequency should be 19.2MHz.88 minItems: 189 maxItems: 990 91 clock-names:92 minItems: 193 maxItems: 994 95 resets:96 maxItems: 197 98 interconnects:99 maxItems: 2100 101 interconnect-names:102 items:103 - const: usb-ddr104 - const: apps-usb105 106 interrupts:107 description: |108 Different types of interrupts are used based on HS PHY used on target:109 - pwr_event: Used for wakeup based on other power events.110 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is111 hs_phy_irq which is not triggered by default and its112 functionality is mutually exclusive to that of113 {dp/dm}_hs_phy_irq and qusb2_phy_irq.114 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and115 expose only a single IRQ whose behavior can be modified116 by the QUSB2PHY_INTR_CTRL register. The required DPSE/117 DMSE configuration is done in QUSB2PHY_INTR_CTRL register118 of PHY address space.119 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/120 DM pads of the SoC. These are used for wakeup121 only on SoCs with non-QUSB2 targets with122 exception of SDM670/SDM845/SM6350.123 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.124 minItems: 2125 maxItems: 18126 127 interrupt-names:128 minItems: 2129 maxItems: 18130 131 qcom,select-utmi-as-pipe-clk:132 description:133 If present, disable USB3 pipe_clk requirement.134 Used when dwc3 operates without SSPHY and only135 HS/FS/LS modes are supported.136 type: boolean137 138 wakeup-source: true139 140# Required child node:141 142patternProperties:143 "^usb@[0-9a-f]+$":144 $ref: snps,dwc3.yaml#145 unevaluatedProperties: false146 147 properties:148 wakeup-source: false149 150required:151 - compatible152 - reg153 - "#address-cells"154 - "#size-cells"155 - ranges156 - clocks157 - clock-names158 - interrupts159 - interrupt-names160 161allOf:162 - if:163 properties:164 compatible:165 contains:166 enum:167 - qcom,ipq4019-dwc3168 - qcom,ipq5332-dwc3169 then:170 properties:171 clocks:172 maxItems: 3173 clock-names:174 items:175 - const: core176 - const: sleep177 - const: mock_utmi178 179 - if:180 properties:181 compatible:182 contains:183 enum:184 - qcom,ipq8064-dwc3185 then:186 properties:187 clocks:188 items:189 - description: Master/Core clock, has to be >= 125 MHz190 for SS operation and >= 60MHz for HS operation.191 clock-names:192 items:193 - const: core194 195 - if:196 properties:197 compatible:198 contains:199 enum:200 - qcom,ipq9574-dwc3201 - qcom,msm8953-dwc3202 - qcom,msm8996-dwc3203 - qcom,msm8998-dwc3204 - qcom,sa8775p-dwc3205 - qcom,sc7180-dwc3206 - qcom,sc7280-dwc3207 - qcom,sdm670-dwc3208 - qcom,sdm845-dwc3209 - qcom,sdx55-dwc3210 - qcom,sdx65-dwc3211 - qcom,sdx75-dwc3212 - qcom,sm6350-dwc3213 then:214 properties:215 clocks:216 maxItems: 5217 clock-names:218 items:219 - const: cfg_noc220 - const: core221 - const: iface222 - const: sleep223 - const: mock_utmi224 225 - if:226 properties:227 compatible:228 contains:229 enum:230 - qcom,ipq6018-dwc3231 then:232 properties:233 clocks:234 minItems: 3235 maxItems: 4236 clock-names:237 oneOf:238 - items:239 - const: core240 - const: sleep241 - const: mock_utmi242 - items:243 - const: cfg_noc244 - const: core245 - const: sleep246 - const: mock_utmi247 248 - if:249 properties:250 compatible:251 contains:252 enum:253 - qcom,ipq8074-dwc3254 - qcom,qdu1000-dwc3255 then:256 properties:257 clocks:258 maxItems: 4259 clock-names:260 items:261 - const: cfg_noc262 - const: core263 - const: sleep264 - const: mock_utmi265 266 - if:267 properties:268 compatible:269 contains:270 enum:271 - qcom,ipq5018-dwc3272 - qcom,msm8994-dwc3273 - qcom,qcs404-dwc3274 then:275 properties:276 clocks:277 maxItems: 4278 clock-names:279 items:280 - const: core281 - const: iface282 - const: sleep283 - const: mock_utmi284 285 - if:286 properties:287 compatible:288 contains:289 enum:290 - qcom,sc8280xp-dwc3291 - qcom,sc8280xp-dwc3-mp292 - qcom,x1e80100-dwc3293 - qcom,x1e80100-dwc3-mp294 then:295 properties:296 clocks:297 maxItems: 9298 clock-names:299 items:300 - const: cfg_noc301 - const: core302 - const: iface303 - const: sleep304 - const: mock_utmi305 - const: noc_aggr306 - const: noc_aggr_north307 - const: noc_aggr_south308 - const: noc_sys309 310 - if:311 properties:312 compatible:313 contains:314 enum:315 - qcom,sdm660-dwc3316 then:317 properties:318 clocks:319 minItems: 4320 maxItems: 5321 clock-names:322 oneOf:323 - items:324 - const: cfg_noc325 - const: core326 - const: iface327 - const: sleep328 - const: mock_utmi329 - items:330 - const: cfg_noc331 - const: core332 - const: sleep333 - const: mock_utmi334 335 - if:336 properties:337 compatible:338 contains:339 enum:340 - qcom,qcm2290-dwc3341 - qcom,sc8180x-dwc3342 - qcom,sc8180x-dwc3-mp343 - qcom,sm6115-dwc3344 - qcom,sm6125-dwc3345 - qcom,sm8150-dwc3346 - qcom,sm8250-dwc3347 - qcom,sm8450-dwc3348 - qcom,sm8550-dwc3349 - qcom,sm8650-dwc3350 then:351 properties:352 clocks:353 minItems: 6354 clock-names:355 items:356 - const: cfg_noc357 - const: core358 - const: iface359 - const: sleep360 - const: mock_utmi361 - const: xo362 363 - if:364 properties:365 compatible:366 contains:367 enum:368 - qcom,sm8350-dwc3369 then:370 properties:371 clocks:372 minItems: 5373 maxItems: 6374 clock-names:375 minItems: 5376 items:377 - const: cfg_noc378 - const: core379 - const: iface380 - const: sleep381 - const: mock_utmi382 - const: xo383 384 - if:385 properties:386 compatible:387 contains:388 enum:389 - qcom,ipq5018-dwc3390 - qcom,ipq6018-dwc3391 - qcom,ipq8074-dwc3392 - qcom,msm8953-dwc3393 - qcom,msm8998-dwc3394 then:395 properties:396 interrupts:397 minItems: 2398 maxItems: 3399 interrupt-names:400 items:401 - const: pwr_event402 - const: qusb2_phy403 - const: ss_phy_irq404 405 - if:406 properties:407 compatible:408 contains:409 enum:410 - qcom,msm8996-dwc3411 - qcom,qcs404-dwc3412 - qcom,sdm660-dwc3413 - qcom,sm6115-dwc3414 - qcom,sm6125-dwc3415 then:416 properties:417 interrupts:418 minItems: 3419 maxItems: 4420 interrupt-names:421 items:422 - const: pwr_event423 - const: qusb2_phy424 - const: hs_phy_irq425 - const: ss_phy_irq426 427 - if:428 properties:429 compatible:430 contains:431 enum:432 - qcom,ipq5332-dwc3433 then:434 properties:435 interrupts:436 maxItems: 3437 interrupt-names:438 items:439 - const: pwr_event440 - const: dp_hs_phy_irq441 - const: dm_hs_phy_irq442 443 - if:444 properties:445 compatible:446 contains:447 enum:448 - qcom,x1e80100-dwc3449 then:450 properties:451 interrupts:452 maxItems: 4453 interrupt-names:454 items:455 - const: pwr_event456 - const: dp_hs_phy_irq457 - const: dm_hs_phy_irq458 - const: ss_phy_irq459 460 - if:461 properties:462 compatible:463 contains:464 enum:465 - qcom,ipq4019-dwc3466 - qcom,ipq8064-dwc3467 - qcom,msm8994-dwc3468 - qcom,qdu1000-dwc3469 - qcom,sa8775p-dwc3470 - qcom,sc7180-dwc3471 - qcom,sc7280-dwc3472 - qcom,sc8180x-dwc3473 - qcom,sc8280xp-dwc3474 - qcom,sdm670-dwc3475 - qcom,sdm845-dwc3476 - qcom,sdx55-dwc3477 - qcom,sdx65-dwc3478 - qcom,sdx75-dwc3479 - qcom,sm4250-dwc3480 - qcom,sm6350-dwc3481 - qcom,sm8150-dwc3482 - qcom,sm8250-dwc3483 - qcom,sm8350-dwc3484 - qcom,sm8450-dwc3485 - qcom,sm8550-dwc3486 - qcom,sm8650-dwc3487 then:488 properties:489 interrupts:490 minItems: 4491 maxItems: 5492 interrupt-names:493 items:494 - const: pwr_event495 - const: hs_phy_irq496 - const: dp_hs_phy_irq497 - const: dm_hs_phy_irq498 - const: ss_phy_irq499 500 - if:501 properties:502 compatible:503 contains:504 enum:505 - qcom,sc8180x-dwc3-mp506 - qcom,x1e80100-dwc3-mp507 then:508 properties:509 interrupts:510 minItems: 10511 maxItems: 10512 interrupt-names:513 items:514 - const: pwr_event_1515 - const: pwr_event_2516 - const: hs_phy_1517 - const: hs_phy_2518 - const: dp_hs_phy_1519 - const: dm_hs_phy_1520 - const: dp_hs_phy_2521 - const: dm_hs_phy_2522 - const: ss_phy_1523 - const: ss_phy_2524 525 - if:526 properties:527 compatible:528 contains:529 enum:530 - qcom,sc8280xp-dwc3-mp531 then:532 properties:533 interrupts:534 minItems: 18535 maxItems: 18536 interrupt-names:537 items:538 - const: pwr_event_1539 - const: pwr_event_2540 - const: pwr_event_3541 - const: pwr_event_4542 - const: hs_phy_1543 - const: hs_phy_2544 - const: hs_phy_3545 - const: hs_phy_4546 - const: dp_hs_phy_1547 - const: dm_hs_phy_1548 - const: dp_hs_phy_2549 - const: dm_hs_phy_2550 - const: dp_hs_phy_3551 - const: dm_hs_phy_3552 - const: dp_hs_phy_4553 - const: dm_hs_phy_4554 - const: ss_phy_1555 - const: ss_phy_2556 557additionalProperties: false558 559examples:560 - |561 #include <dt-bindings/clock/qcom,gcc-sdm845.h>562 #include <dt-bindings/interrupt-controller/arm-gic.h>563 #include <dt-bindings/interrupt-controller/irq.h>564 soc {565 #address-cells = <2>;566 #size-cells = <2>;567 568 usb@a6f8800 {569 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";570 reg = <0 0x0a6f8800 0 0x400>;571 572 #address-cells = <2>;573 #size-cells = <2>;574 ranges;575 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,576 <&gcc GCC_USB30_PRIM_MASTER_CLK>,577 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,578 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,579 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;580 clock-names = "cfg_noc",581 "core",582 "iface",583 "sleep",584 "mock_utmi";585 586 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,587 <&gcc GCC_USB30_PRIM_MASTER_CLK>;588 assigned-clock-rates = <19200000>, <150000000>;589 590 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,591 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,592 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,593 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,594 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;595 interrupt-names = "pwr_event", "hs_phy_irq",596 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";597 598 power-domains = <&gcc USB30_PRIM_GDSC>;599 600 resets = <&gcc GCC_USB30_PRIM_BCR>;601 602 usb@a600000 {603 compatible = "snps,dwc3";604 reg = <0 0x0a600000 0 0xcd00>;605 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;606 iommus = <&apps_smmu 0x740 0>;607 snps,dis_u2_susphy_quirk;608 snps,dis_enblslpm_quirk;609 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;610 phy-names = "usb2-phy", "usb3-phy";611 };612 };613 };614