63 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cadence watchdog timer controller8 9maintainers:10 - Neeli Srinivas <srinivas.neeli@amd.com>11 12description:13 The cadence watchdog timer is used to detect and recover from14 system malfunctions. This watchdog contains 24 bit counter and15 a programmable reset period. The timeout period varies from 1 ms16 to 30 seconds while using a 100Mhz clock.17 18allOf:19 - $ref: watchdog.yaml#20 21properties:22 compatible:23 enum:24 - cdns,wdt-r1p225 26 reg:27 maxItems: 128 29 clocks:30 maxItems: 131 32 interrupts:33 maxItems: 134 35 reset-on-timeout:36 type: boolean37 description: |38 If this property exists, then a reset is done when watchdog39 times out.40 41required:42 - compatible43 - reg44 - clocks45 - interrupts46 47unevaluatedProperties: false48 49examples:50 - |51 #include <dt-bindings/interrupt-controller/arm-gic.h>52 53 watchdog@f8005000 {54 compatible = "cdns,wdt-r1p2";55 reg = <0xf8005000 0x1000>;56 clocks = <&clkc 45>;57 interrupt-parent = <&intc>;58 interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>;59 reset-on-timeout;60 timeout-sec = <10>;61 };62...63