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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek SoCs Watchdog timer8 9maintainers:10 - Matthias Brugger <matthias.bgg@gmail.com>11 12description:13 The watchdog supports a pre-timeout interrupt that fires14 timeout-sec/2 before the expiry.15 16allOf:17 - $ref: watchdog.yaml#18 19properties:20 compatible:21 oneOf:22 - enum:23 - mediatek,mt2712-wdt24 - mediatek,mt6589-wdt25 - mediatek,mt6735-wdt26 - mediatek,mt6795-wdt27 - mediatek,mt7986-wdt28 - mediatek,mt7988-wdt29 - mediatek,mt8183-wdt30 - mediatek,mt8186-wdt31 - mediatek,mt8188-wdt32 - mediatek,mt8192-wdt33 - mediatek,mt8195-wdt34 - items:35 - enum:36 - mediatek,mt2701-wdt37 - mediatek,mt6582-wdt38 - mediatek,mt6797-wdt39 - mediatek,mt7622-wdt40 - mediatek,mt7623-wdt41 - mediatek,mt7629-wdt42 - mediatek,mt8173-wdt43 - mediatek,mt8365-wdt44 - mediatek,mt8516-wdt45 - const: mediatek,mt6589-wdt46 47 reg:48 maxItems: 149 50 interrupts:51 items:52 - description: Watchdog pre-timeout (bark) interrupt53 54 mediatek,disable-extrst:55 description: Disable sending output reset signal56 type: boolean57 58 mediatek,reset-by-toprgu:59 description: The Top Reset Generation Unit (TOPRGU) generates reset signals60 and distributes them to each IP. If present, the watchdog timer will be61 reset by TOPRGU once system resets.62 type: boolean63 64 '#reset-cells':65 const: 166 67required:68 - compatible69 - reg70 71unevaluatedProperties: false72 73examples:74 - |75 #include <dt-bindings/interrupt-controller/arm-gic.h>76 77 soc {78 #address-cells = <2>;79 #size-cells = <2>;80 81 watchdog: watchdog@10007000 {82 compatible = "mediatek,mt8183-wdt";83 reg = <0 0x10007000 0 0x100>;84 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;85 mediatek,disable-extrst;86 timeout-sec = <10>;87 #reset-cells = <1>;88 };89 };90