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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer8 9maintainers:10 - Rajendra Nayak <quic_rjendra@quicinc.com>11 12properties:13 $nodename:14 pattern: "^(watchdog|timer)@[0-9a-f]+$"15 16 compatible:17 oneOf:18 - items:19 - enum:20 - qcom,kpss-wdt-ipq401921 - qcom,apss-wdt-ipq501822 - qcom,apss-wdt-ipq533223 - qcom,apss-wdt-ipq957424 - qcom,apss-wdt-msm822625 - qcom,apss-wdt-msm897426 - qcom,apss-wdt-msm899427 - qcom,apss-wdt-qcm229028 - qcom,apss-wdt-qcs40429 - qcom,apss-wdt-sa8255p30 - qcom,apss-wdt-sa8775p31 - qcom,apss-wdt-sc718032 - qcom,apss-wdt-sc728033 - qcom,apss-wdt-sc8180x34 - qcom,apss-wdt-sc8280xp35 - qcom,apss-wdt-sdm84536 - qcom,apss-wdt-sdx5537 - qcom,apss-wdt-sdx6538 - qcom,apss-wdt-sm611539 - qcom,apss-wdt-sm635040 - qcom,apss-wdt-sm815041 - qcom,apss-wdt-sm825042 - const: qcom,kpss-wdt43 - const: qcom,kpss-wdt44 deprecated: true45 - items:46 - const: qcom,scss-timer47 - const: qcom,msm-timer48 - items:49 - enum:50 - qcom,kpss-wdt-apq806451 - qcom,kpss-wdt-ipq806452 - qcom,kpss-wdt-mdm961553 - qcom,kpss-wdt-msm896054 - const: qcom,kpss-timer55 - const: qcom,msm-timer56 57 reg:58 maxItems: 159 60 clocks:61 maxItems: 162 63 clock-names:64 items:65 - const: sleep66 67 clock-frequency:68 description:69 The frequency of the general purpose timer in Hz.70 71 cpu-offset:72 $ref: /schemas/types.yaml#/definitions/uint3273 description:74 Per-CPU offset used when the timer is accessed without the CPU remapping75 facilities. The offset is cpu-offset + (0x10000 * cpu-nr).76 77 interrupts:78 minItems: 179 maxItems: 580 81required:82 - compatible83 - reg84 - clocks85 86allOf:87 - $ref: watchdog.yaml#88 89 - if:90 properties:91 compatible:92 contains:93 const: qcom,kpss-wdt94 then:95 properties:96 clock-frequency: false97 cpu-offset: false98 interrupts:99 minItems: 1100 items:101 - description: Bark102 - description: Bite103 104 else:105 properties:106 interrupts:107 minItems: 3108 items:109 - description: Debug110 - description: First general purpose timer111 - description: Second general purpose timer112 - description: First watchdog113 - description: Second watchdog114 required:115 - clock-frequency116 117unevaluatedProperties: false118 119examples:120 - |121 #include <dt-bindings/interrupt-controller/arm-gic.h>122 123 watchdog@17c10000 {124 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";125 reg = <0x17c10000 0x1000>;126 clocks = <&sleep_clk>;127 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;128 timeout-sec = <10>;129 };130 131 - |132 #include <dt-bindings/interrupt-controller/arm-gic.h>133 134 watchdog@200a000 {135 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";136 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,137 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,138 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,139 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,140 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;141 reg = <0x0200a000 0x100>;142 clock-frequency = <25000000>;143 clocks = <&sleep_clk>;144 clock-names = "sleep";145 cpu-offset = <0x80000>;146 };147