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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Realtek Otto watchdog timer8 9maintainers:10 - Sander Vanheule <sander@svanheule.net>11 12description: |13 The timer has two timeout phases. Both phases have a maximum duration of 3214 prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The15 minimum duration of each phase is one tick. Each phase can trigger an16 interrupt, although the phase 2 interrupt will occur with the system reset.17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the19 system some time to clean up, or notify others that it's going to reset.20 During this phase, pinging the WDT has no effect, and a reset is21 unavoidable, unless the WDT is disabled.22 23allOf:24 - $ref: watchdog.yaml#25 26properties:27 compatible:28 enum:29 - realtek,rtl8380-wdt30 - realtek,rtl8390-wdt31 - realtek,rtl9300-wdt32 - realtek,rtl9310-wdt33 34 reg:35 maxItems: 136 37 clocks:38 maxItems: 139 40 interrupts:41 items:42 - description: interrupt specifier for pretimeout43 - description: interrupt specifier for timeout44 45 interrupt-names:46 items:47 - const: phase148 - const: phase249 50 realtek,reset-mode:51 $ref: /schemas/types.yaml#/definitions/string52 description: |53 Specify how the system is reset after a timeout. Defaults to "cpu" if54 left unspecified.55 oneOf:56 - description: Reset the entire chip57 const: soc58 - description: |59 Reset the CPU and IPsec engine, but leave other peripherals untouched60 const: cpu61 - description: |62 Reset the execution pointer, but don't actually reset any hardware63 const: software64 65required:66 - compatible67 - reg68 - clocks69 - interrupts70 - interrupt-names71 72unevaluatedProperties: false73 74examples:75 - |76 watchdog: watchdog@3150 {77 compatible = "realtek,rtl8380-wdt";78 reg = <0x3150 0xc>;79 80 realtek,reset-mode = "soc";81 82 clocks = <&lxbus_clock>;83 timeout-sec = <20>;84 85 interrupt-parent = <&rtlintc>;86 interrupt-names = "phase1", "phase2";87 interrupts = <19>, <18>;88 };89 90...91