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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: StarFive Watchdog for JH7100 and JH7110 SoC8 9maintainers:10 - Xingyu Wu <xingyu.wu@starfivetech.com>11 - Samin Guo <samin.guo@starfivetech.com>12 13description:14 The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog15 has only one timeout phase and reboots. And JH7110 watchdog has two16 timeout phases. At the first phase, the signal of watchdog interrupt17 output(WDOGINT) will rise when counter is 0. The counter will reload18 the timeout value. And then, if counter decreases to 0 again and WDOGINT19 isn't cleared, the watchdog will reset the system unless the watchdog20 reset is disabled.21 22properties:23 compatible:24 oneOf:25 - enum:26 - starfive,jh7100-wdt27 - starfive,jh7110-wdt28 - items:29 - enum:30 - starfive,jh8100-wdt31 - const: starfive,jh7110-wdt32 33 reg:34 maxItems: 135 36 interrupts:37 maxItems: 138 39 clocks:40 items:41 - description: APB clock42 - description: Core clock43 44 clock-names:45 items:46 - const: apb47 - const: core48 49 resets:50 minItems: 151 maxItems: 252 53required:54 - compatible55 - reg56 - clocks57 - clock-names58 - resets59 60allOf:61 - $ref: watchdog.yaml#62 63 - if:64 properties:65 compatible:66 contains:67 enum:68 - starfive,jh8100-wdt69 then:70 properties:71 resets:72 items:73 - description: Core reset74 else:75 properties:76 resets:77 items:78 - description: APB reset79 - description: Core reset80 81unevaluatedProperties: false82 83examples:84 - |85 watchdog@12480000 {86 compatible = "starfive,jh7100-wdt";87 reg = <0x12480000 0x10000>;88 clocks = <&clk 171>,89 <&clk 172>;90 clock-names = "apb", "core";91 resets = <&rst 99>,92 <&rst 100>;93 };94