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1CE4100 Device Tree Bindings2---------------------------3 4The CE4100 SoC uses for in core peripherals the following compatible5format: <vendor>,<chip>-<device>.6Many of the "generic" devices like HPET or IO APIC have the ce41007name in their compatible property because they first appeared in this8SoC.9 10The CPU nodes11-------------12 13 cpus {14 #address-cells = <1>;15 #size-cells = <0>;16 17 cpu@0 {18 device_type = "cpu";19 compatible = "intel,ce4100";20 reg = <0x00>;21 };22 23 cpu@2 {24 device_type = "cpu";25 compatible = "intel,ce4100";26 reg = <0x02>;27 };28 };29 30A "cpu" node describes one logical processor (hardware thread).31 32Required properties:33 34- device_type35 Device type, must be "cpu".36 37- reg38 Local APIC ID, the unique number assigned to each processor by39 system hardware.40 41The SoC node42------------43 44This node describes the in-core peripherals. Required property:45 compatible = "intel,ce4100-cp";46 47The PCI node48------------49This node describes the PCI bus on the SoC. Its property should be50 compatible = "intel,ce4100-pci", "pci";51 52If the OS is using the IO-APIC for interrupt routing then the reported53interrupt numbers for devices is no longer true. In order to obtain the54correct interrupt number, the child node which represents the device has55to contain the interrupt property. Besides the interrupt property it has56to contain at least the reg property containing the PCI bus address and57compatible property according to "PCI Bus Binding Revision 2.1".58