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1.. SPDX-License-Identifier: GPL-2.02.. include:: <isonum.txt>3 4===========================================5Compute Express Link Subsystem Maturity Map6===========================================7 8The Linux CXL subsystem tracks the dynamic `CXL specification9<https://computeexpresslink.org/cxl-specification-landing-page>`_ that10continues to respond to new use cases with new features, capability11updates and fixes. At any given point some aspects of the subsystem are12more mature than others. While the periodic pull requests summarize the13`work being incorporated each merge window14<https://lore.kernel.org/linux-cxl/?q=s%3APULL+s%3ACXL+tc%3Atorvalds+NOT+s%3ARe>`_,15those do not always convey progress relative to a starting point and a16future end goal.17 18What follows is a coarse breakdown of the subsystem's major19responsibilities along with a maturity score. The expectation is that20the change-history of this document provides an overview summary of the21subsystem maturation over time.22 23The maturity scores are:24 25- [3] Mature: Work in this area is complete and no changes on the horizon.26 Note that this score can regress from one kernel release to the next27 based on new test results or end user reports.28 29- [2] Stabilizing: Major functionality operational, common cases are30 mature, but known corner cases are still a work in progress.31 32- [1] Initial: Capability that has exited the Proof of Concept phase, but33 may still have significant gaps to close and fixes to apply as real34 world testing occurs.35 36- [0] Known gap: Feature is on a medium to long term horizon to37 implement. If the specification has a feature that does not even have38 a '0' score in this document, there is a good chance that no one in39 the linux-cxl@vger.kernel.org community has started to look at it.40 41- X: Out of scope for kernel enabling, or kernel enabling not required42 43Feature and Capabilities44========================45 46Enumeration / Provisioning47--------------------------48All of the fundamental enumeration an object model of the subsystem is49in place, but there are several corner cases that are pending closure.50 51 52* [2] CXL Window Enumeration53 54 * [0] :ref:`Extended-linear memory-side cache <extended-linear>`55 * [0] Low Memory-hole56 * [0] Hetero-interleave57 58* [2] Switch Enumeration59 60 * [0] CXL register enumeration link-up dependency61 62* [2] HDM Decoder Configuration63 64 * [0] Decoder target and granularity constraints65 66* [2] Performance enumeration67 68 * [3] Endpoint CDAT69 * [3] Switch CDAT70 * [1] CDAT to Core-mm integration71 72 * [1] x8673 * [0] Arm6474 * [0] All other arch.75 76 * [0] Shared link77 78* [2] Hotplug79 (see CXL Window Enumeration)80 81 * [0] Handle Soft Reserved conflicts82 83* [0] :ref:`RCH link status <rch-link-status>`84* [0] Fabrics / G-FAM (chapter 7)85* [0] Global Access Endpoint86 87 88RAS89---90In many ways CXL can be seen as a standardization of what would normally91be handled by custom EDAC drivers. The open development here is92mainly caused by the enumeration corner cases above.93 94* [3] Component events (OS)95* [2] Component events (FFM)96* [1] Endpoint protocol errors (OS)97* [1] Endpoint protocol errors (FFM)98* [0] Switch protocol errors (OS)99* [1] Switch protocol errors (FFM)100* [2] DPA->HPA Address translation101 102 * [1] XOR Interleave translation103 (see CXL Window Enumeration)104 105* [1] Memory Failure coordination106* [0] Scrub control107* [2] ACPI error injection EINJ108 109 * [0] EINJ v2110 * [X] Compliance DOE111 112* [2] Native error injection113* [3] RCH error handling114* [1] VH error handling115* [0] PPR116* [0] Sparing117* [0] Device built in test118 119 120Mailbox commands121----------------122 123* [3] Firmware update124* [3] Health / Alerts125* [1] :ref:`Background commands <background-commands>`126* [3] Sanitization127* [3] Security commands128* [3] RAW Command Debug Passthrough129* [0] CEL-only-validation Passthrough130* [0] Switch CCI131* [3] Timestamp132* [1] PMEM labels133* [0] PMEM GPF / Dirty Shutdown134* [0] Scan Media135 136PMU137---138* [1] Type 3 PMU139* [0] Switch USP/ DSP, Root Port140 141Security142--------143 144* [X] CXL Trusted Execution Environment Security Protocol (TSP)145* [X] CXL IDE (subsumed by TSP)146 147Memory-pooling148--------------149 150* [1] Hotplug of LDs (via PCI hotplug)151* [0] Dynamic Capacity Device (DCD) Support152 153Multi-host sharing154------------------155 156* [0] Hardware coherent shared memory157* [0] Software managed coherency shared memory158 159Multi-host memory160-----------------161 162* [0] Dynamic Capacity Device Support163* [0] Sharing164 165Accelerator166-----------167 168* [0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2)169* [0] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2)170* [0] CXL.cache 68b (CXL 2.0)171* [0] CXL.cache 256b Cache IDs (CXL 3.0)172 173User Flow Support174-----------------175 176* [0] HPA->DPA Address translation (need xormaps export solution)177 178Details179=======180 181.. _extended-linear:182 183* **Extended-linear memory-side cache**: An HMAT proposal to enumerate the presence of a184 memory-side cache where the cache capacity extends the SRAT address185 range capacity. `See the ECN186 <https://lore.kernel.org/linux-cxl/6650e4f835a0e_195e294a8@dwillia2-mobl3.amr.corp.intel.com.notmuch/>`_187 for more details:188 189.. _rch-link-status:190 191* **RCH Link Status**: RCH (Restricted CXL Host) topologies, end up192 hiding some standard registers like PCIe Link Status / Capabilities in193 the CXL RCRB (Root Complex Register Block).194 195.. _background-commands:196 197* **Background commands**: The CXL background command mechanism is198 awkward as the single slot is monopolized potentially indefinitely by199 various commands. A `cancel on conflict200 <http://lore.kernel.org/r/66035c2e8ba17_770232948b@dwillia2-xfh.jf.intel.com.notmuch>`_201 facility is needed to make sure the kernel can ensure forward progress202 of priority commands.203