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1==================================2DMAengine controller documentation3==================================4 5Hardware Introduction6=====================7 8Most of the Slave DMA controllers have the same general principles of9operations.10 11They have a given number of channels to use for the DMA transfers, and12a given number of requests lines.13 14Requests and channels are pretty much orthogonal. Channels can be used15to serve several to any requests. To simplify, channels are the16entities that will be doing the copy, and requests what endpoints are17involved.18 19The request lines actually correspond to physical lines going from the20DMA-eligible devices to the controller itself. Whenever the device21will want to start a transfer, it will assert a DMA request (DRQ) by22asserting that request line.23 24A very simple DMA controller would only take into account a single25parameter: the transfer size. At each clock cycle, it would transfer a26byte of data from one buffer to another, until the transfer size has27been reached.28 29That wouldn't work well in the real world, since slave devices might30require a specific number of bits to be transferred in a single31cycle. For example, we may want to transfer as much data as the32physical bus allows to maximize performances when doing a simple33memory copy operation, but our audio device could have a narrower FIFO34that requires data to be written exactly 16 or 24 bits at a time. This35is why most if not all of the DMA controllers can adjust this, using a36parameter called the transfer width.37 38Moreover, some DMA controllers, whenever the RAM is used as a source39or destination, can group the reads or writes in memory into a buffer,40so instead of having a lot of small memory accesses, which is not41really efficient, you'll get several bigger transfers. This is done42using a parameter called the burst size, that defines how many single43reads/writes it's allowed to do without the controller splitting the44transfer into smaller sub-transfers.45 46Our theoretical DMA controller would then only be able to do transfers47that involve a single contiguous block of data. However, some of the48transfers we usually have are not, and want to copy data from49non-contiguous buffers to a contiguous buffer, which is called50scatter-gather.51 52DMAEngine, at least for mem2dev transfers, require support for53scatter-gather. So we're left with two cases here: either we have a54quite simple DMA controller that doesn't support it, and we'll have to55implement it in software, or we have a more advanced DMA controller,56that implements in hardware scatter-gather.57 58The latter are usually programmed using a collection of chunks to59transfer, and whenever the transfer is started, the controller will go60over that collection, doing whatever we programmed there.61 62This collection is usually either a table or a linked list. You will63then push either the address of the table and its number of elements,64or the first item of the list to one channel of the DMA controller,65and whenever a DRQ will be asserted, it will go through the collection66to know where to fetch the data from.67 68Either way, the format of this collection is completely dependent on69your hardware. Each DMA controller will require a different structure,70but all of them will require, for every chunk, at least the source and71destination addresses, whether it should increment these addresses or72not and the three parameters we saw earlier: the burst size, the73transfer width and the transfer size.74 75The one last thing is that usually, slave devices won't issue DRQ by76default, and you have to enable this in your slave device driver first77whenever you're willing to use DMA.78 79These were just the general memory-to-memory (also called mem2mem) or80memory-to-device (mem2dev) kind of transfers. Most devices often81support other kind of transfers or memory operations that dmaengine82support and will be detailed later in this document.83 84DMA Support in Linux85====================86 87Historically, DMA controller drivers have been implemented using the88async TX API, to offload operations such as memory copy, XOR,89cryptography, etc., basically any memory to memory operation.90 91Over time, the need for memory to device transfers arose, and92dmaengine was extended. Nowadays, the async TX API is written as a93layer on top of dmaengine, and acts as a client. Still, dmaengine94accommodates that API in some cases, and made some design choices to95ensure that it stayed compatible.96 97For more information on the Async TX API, please look the relevant98documentation file in Documentation/crypto/async-tx-api.rst.99 100DMAEngine APIs101==============102 103``struct dma_device`` Initialization104------------------------------------105 106Just like any other kernel framework, the whole DMAEngine registration107relies on the driver filling a structure and registering against the108framework. In our case, that structure is dma_device.109 110The first thing you need to do in your driver is to allocate this111structure. Any of the usual memory allocators will do, but you'll also112need to initialize a few fields in there:113 114- ``channels``: should be initialized as a list using the115 INIT_LIST_HEAD macro for example116 117- ``src_addr_widths``:118 should contain a bitmask of the supported source transfer width119 120- ``dst_addr_widths``:121 should contain a bitmask of the supported destination transfer width122 123- ``directions``:124 should contain a bitmask of the supported slave directions125 (i.e. excluding mem2mem transfers)126 127- ``residue_granularity``:128 granularity of the transfer residue reported to dma_set_residue.129 This can be either:130 131 - Descriptor:132 your device doesn't support any kind of residue133 reporting. The framework will only know that a particular134 transaction descriptor is done.135 136 - Segment:137 your device is able to report which chunks have been transferred138 139 - Burst:140 your device is able to report which burst have been transferred141 142- ``dev``: should hold the pointer to the ``struct device`` associated143 to your current driver instance.144 145Supported transaction types146---------------------------147 148The next thing you need is to set which transaction types your device149(and driver) supports.150 151Our ``dma_device structure`` has a field called cap_mask that holds the152various types of transaction supported, and you need to modify this153mask using the dma_cap_set function, with various flags depending on154transaction types you support as an argument.155 156All those capabilities are defined in the ``dma_transaction_type enum``,157in ``include/linux/dmaengine.h``158 159Currently, the types available are:160 161- DMA_MEMCPY162 163 - The device is able to do memory to memory copies164 165 - No matter what the overall size of the combined chunks for source and166 destination is, only as many bytes as the smallest of the two will be167 transmitted. That means the number and size of the scatter-gather buffers in168 both lists need not be the same, and that the operation functionally is169 equivalent to a ``strncpy`` where the ``count`` argument equals the smallest170 total size of the two scatter-gather list buffers.171 172 - It's usually used for copying pixel data between host memory and173 memory-mapped GPU device memory, such as found on modern PCI video graphics174 cards. The most immediate example is the OpenGL API function175 ``glReadPielx()``, which might require a verbatim copy of a huge framebuffer176 from local device memory onto host memory.177 178- DMA_XOR179 180 - The device is able to perform XOR operations on memory areas181 182 - Used to accelerate XOR intensive tasks, such as RAID5183 184- DMA_XOR_VAL185 186 - The device is able to perform parity check using the XOR187 algorithm against a memory buffer.188 189- DMA_PQ190 191 - The device is able to perform RAID6 P+Q computations, P being a192 simple XOR, and Q being a Reed-Solomon algorithm.193 194- DMA_PQ_VAL195 196 - The device is able to perform parity check using RAID6 P+Q197 algorithm against a memory buffer.198 199- DMA_MEMSET200 201 - The device is able to fill memory with the provided pattern202 203 - The pattern is treated as a single byte signed value.204 205- DMA_INTERRUPT206 207 - The device is able to trigger a dummy transfer that will208 generate periodic interrupts209 210 - Used by the client drivers to register a callback that will be211 called on a regular basis through the DMA controller interrupt212 213- DMA_PRIVATE214 215 - The devices only supports slave transfers, and as such isn't216 available for async transfers.217 218- DMA_ASYNC_TX219 220 - Must not be set by the device, and will be set by the framework221 if needed222 223 - TODO: What is it about?224 225- DMA_SLAVE226 227 - The device can handle device to memory transfers, including228 scatter-gather transfers.229 230 - While in the mem2mem case we were having two distinct types to231 deal with a single chunk to copy or a collection of them, here,232 we just have a single transaction type that is supposed to233 handle both.234 235 - If you want to transfer a single contiguous memory buffer,236 simply build a scatter list with only one item.237 238- DMA_CYCLIC239 240 - The device can handle cyclic transfers.241 242 - A cyclic transfer is a transfer where the chunk collection will243 loop over itself, with the last item pointing to the first.244 245 - It's usually used for audio transfers, where you want to operate246 on a single ring buffer that you will fill with your audio data.247 248- DMA_INTERLEAVE249 250 - The device supports interleaved transfer.251 252 - These transfers can transfer data from a non-contiguous buffer253 to a non-contiguous buffer, opposed to DMA_SLAVE that can254 transfer data from a non-contiguous data set to a continuous255 destination buffer.256 257 - It's usually used for 2d content transfers, in which case you258 want to transfer a portion of uncompressed data directly to the259 display to print it260 261- DMA_COMPLETION_NO_ORDER262 263 - The device does not support in order completion.264 265 - The driver should return DMA_OUT_OF_ORDER for device_tx_status if266 the device is setting this capability.267 268 - All cookie tracking and checking API should be treated as invalid if269 the device exports this capability.270 271 - At this point, this is incompatible with polling option for dmatest.272 273 - If this cap is set, the user is recommended to provide an unique274 identifier for each descriptor sent to the DMA device in order to275 properly track the completion.276 277- DMA_REPEAT278 279 - The device supports repeated transfers. A repeated transfer, indicated by280 the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that281 it gets automatically repeated when it ends, but can additionally be282 replaced by the client.283 284 - This feature is limited to interleaved transfers, this flag should thus not285 be set if the DMA_INTERLEAVE flag isn't set. This limitation is based on286 the current needs of DMA clients, support for additional transfer types287 should be added in the future if and when the need arises.288 289- DMA_LOAD_EOT290 291 - The device supports replacing repeated transfers at end of transfer (EOT)292 by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set.293 294 - Support for replacing a currently running transfer at another point (such295 as end of burst instead of end of transfer) will be added in the future296 based on DMA clients needs, if and when the need arises.297 298These various types will also affect how the source and destination299addresses change over time.300 301Addresses pointing to RAM are typically incremented (or decremented)302after each transfer. In case of a ring buffer, they may loop303(DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO)304are typically fixed.305 306Per descriptor metadata support307-------------------------------308Some data movement architecture (DMA controller and peripherals) uses metadata309associated with a transaction. The DMA controller role is to transfer the310payload and the metadata alongside.311The metadata itself is not used by the DMA engine itself, but it contains312parameters, keys, vectors, etc for peripheral or from the peripheral.313 314The DMAengine framework provides a generic ways to facilitate the metadata for315descriptors. Depending on the architecture the DMA driver can implement either316or both of the methods and it is up to the client driver to choose which one317to use.318 319- DESC_METADATA_CLIENT320 321 The metadata buffer is allocated/provided by the client driver and it is322 attached (via the dmaengine_desc_attach_metadata() helper to the descriptor.323 324 From the DMA driver the following is expected for this mode:325 326 - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM327 328 The data from the provided metadata buffer should be prepared for the DMA329 controller to be sent alongside of the payload data. Either by copying to a330 hardware descriptor, or highly coupled packet.331 332 - DMA_DEV_TO_MEM333 334 On transfer completion the DMA driver must copy the metadata to the client335 provided metadata buffer before notifying the client about the completion.336 After the transfer completion, DMA drivers must not touch the metadata337 buffer provided by the client.338 339- DESC_METADATA_ENGINE340 341 The metadata buffer is allocated/managed by the DMA driver. The client driver342 can ask for the pointer, maximum size and the currently used size of the343 metadata and can directly update or read it. dmaengine_desc_get_metadata_ptr()344 and dmaengine_desc_set_metadata_len() is provided as helper functions.345 346 From the DMA driver the following is expected for this mode:347 348 - get_metadata_ptr()349 350 Should return a pointer for the metadata buffer, the maximum size of the351 metadata buffer and the currently used / valid (if any) bytes in the buffer.352 353 - set_metadata_len()354 355 It is called by the clients after it have placed the metadata to the buffer356 to let the DMA driver know the number of valid bytes provided.357 358 Note: since the client will ask for the metadata pointer in the completion359 callback (in DMA_DEV_TO_MEM case) the DMA driver must ensure that the360 descriptor is not freed up prior the callback is called.361 362Device operations363-----------------364 365Our dma_device structure also requires a few function pointers in366order to implement the actual logic, now that we described what367operations we were able to perform.368 369The functions that we have to fill in there, and hence have to370implement, obviously depend on the transaction types you reported as371supported.372 373- ``device_alloc_chan_resources``374 375- ``device_free_chan_resources``376 377 - These functions will be called whenever a driver will call378 ``dma_request_channel`` or ``dma_release_channel`` for the first/last379 time on the channel associated to that driver.380 381 - They are in charge of allocating/freeing all the needed382 resources in order for that channel to be useful for your driver.383 384 - These functions can sleep.385 386- ``device_prep_dma_*``387 388 - These functions are matching the capabilities you registered389 previously.390 391 - These functions all take the buffer or the scatterlist relevant392 for the transfer being prepared, and should create a hardware393 descriptor or a list of hardware descriptors from it394 395 - These functions can be called from an interrupt context396 397 - Any allocation you might do should be using the GFP_NOWAIT398 flag, in order not to potentially sleep, but without depleting399 the emergency pool either.400 401 - Drivers should try to pre-allocate any memory they might need402 during the transfer setup at probe time to avoid putting to403 much pressure on the nowait allocator.404 405 - It should return a unique instance of the406 ``dma_async_tx_descriptor structure``, that further represents this407 particular transfer.408 409 - This structure can be initialized using the function410 ``dma_async_tx_descriptor_init``.411 412 - You'll also need to set two fields in this structure:413 414 - flags:415 TODO: Can it be modified by the driver itself, or416 should it be always the flags passed in the arguments417 418 - tx_submit: A pointer to a function you have to implement,419 that is supposed to push the current transaction descriptor to a420 pending queue, waiting for issue_pending to be called.421 422 - In this structure the function pointer callback_result can be423 initialized in order for the submitter to be notified that a424 transaction has completed. In the earlier code the function pointer425 callback has been used. However it does not provide any status to the426 transaction and will be deprecated. The result structure defined as427 ``dmaengine_result`` that is passed in to callback_result428 has two fields:429 430 - result: This provides the transfer result defined by431 ``dmaengine_tx_result``. Either success or some error condition.432 433 - residue: Provides the residue bytes of the transfer for those that434 support residue.435 436- ``device_prep_peripheral_dma_vec``437 438 - Similar to ``device_prep_slave_sg``, but it takes a pointer to a439 array of ``dma_vec`` structures, which (in the long run) will replace440 scatterlists.441 442- ``device_issue_pending``443 444 - Takes the first transaction descriptor in the pending queue,445 and starts the transfer. Whenever that transfer is done, it446 should move to the next transaction in the list.447 448 - This function can be called in an interrupt context449 450- ``device_tx_status``451 452 - Should report the bytes left to go over on the given channel453 454 - Should only care about the transaction descriptor passed as455 argument, not the currently active one on a given channel456 457 - The tx_state argument might be NULL458 459 - Should use dma_set_residue to report it460 461 - In the case of a cyclic transfer, it should only take into462 account the total size of the cyclic buffer.463 464 - Should return DMA_OUT_OF_ORDER if the device does not support in order465 completion and is completing the operation out of order.466 467 - This function can be called in an interrupt context.468 469- device_config470 471 - Reconfigures the channel with the configuration given as argument472 473 - This command should NOT perform synchronously, or on any474 currently queued transfers, but only on subsequent ones475 476 - In this case, the function will receive a ``dma_slave_config``477 structure pointer as an argument, that will detail which478 configuration to use.479 480 - Even though that structure contains a direction field, this481 field is deprecated in favor of the direction argument given to482 the prep_* functions483 484 - This call is mandatory for slave operations only. This should NOT be485 set or expected to be set for memcpy operations.486 If a driver support both, it should use this call for slave487 operations only and not for memcpy ones.488 489- device_pause490 491 - Pauses a transfer on the channel492 493 - This command should operate synchronously on the channel,494 pausing right away the work of the given channel495 496- device_resume497 498 - Resumes a transfer on the channel499 500 - This command should operate synchronously on the channel,501 resuming right away the work of the given channel502 503- device_terminate_all504 505 - Aborts all the pending and ongoing transfers on the channel506 507 - For aborted transfers the complete callback should not be called508 509 - Can be called from atomic context or from within a complete510 callback of a descriptor. Must not sleep. Drivers must be able511 to handle this correctly.512 513 - Termination may be asynchronous. The driver does not have to514 wait until the currently active transfer has completely stopped.515 See device_synchronize.516 517- device_synchronize518 519 - Must synchronize the termination of a channel to the current520 context.521 522 - Must make sure that memory for previously submitted523 descriptors is no longer accessed by the DMA controller.524 525 - Must make sure that all complete callbacks for previously526 submitted descriptors have finished running and none are527 scheduled to run.528 529 - May sleep.530 531 532Misc notes533==========534 535(stuff that should be documented, but don't really know536where to put them)537 538``dma_run_dependencies``539 540- Should be called at the end of an async TX transfer, and can be541 ignored in the slave transfers case.542 543- Makes sure that dependent operations are run before marking it544 as complete.545 546dma_cookie_t547 548- it's a DMA transaction ID that will increment over time.549 550- Not really relevant any more since the introduction of ``virt-dma``551 that abstracts it away.552 553dma_vec554 555- A small structure that contains a DMA address and length.556 557DMA_CTRL_ACK558 559- If clear, the descriptor cannot be reused by provider until the560 client acknowledges receipt, i.e. has a chance to establish any561 dependency chains562 563- This can be acked by invoking async_tx_ack()564 565- If set, does not mean descriptor can be reused566 567DMA_CTRL_REUSE568 569- If set, the descriptor can be reused after being completed. It should570 not be freed by provider if this flag is set.571 572- The descriptor should be prepared for reuse by invoking573 ``dmaengine_desc_set_reuse()`` which will set DMA_CTRL_REUSE.574 575- ``dmaengine_desc_set_reuse()`` will succeed only when channel support576 reusable descriptor as exhibited by capabilities577 578- As a consequence, if a device driver wants to skip the579 ``dma_map_sg()`` and ``dma_unmap_sg()`` in between 2 transfers,580 because the DMA'd data wasn't used, it can resubmit the transfer right after581 its completion.582 583- Descriptor can be freed in few ways584 585 - Clearing DMA_CTRL_REUSE by invoking586 ``dmaengine_desc_clear_reuse()`` and submitting for last txn587 588 - Explicitly invoking ``dmaengine_desc_free()``, this can succeed only589 when DMA_CTRL_REUSE is already set590 591 - Terminating the channel592 593- DMA_PREP_CMD594 595 - If set, the client driver tells DMA controller that passed data in DMA596 API is command data.597 598 - Interpretation of command data is DMA controller specific. It can be599 used for issuing commands to other peripherals/register reads/register600 writes for which the descriptor should be in different format from601 normal data descriptors.602 603- DMA_PREP_REPEAT604 605 - If set, the transfer will be automatically repeated when it ends until a606 new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag.607 If the next transfer to be queued on the channel does not have the608 DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the609 client terminates all transfers.610 611 - This flag is only supported if the channel reports the DMA_REPEAT612 capability.613 614- DMA_PREP_LOAD_EOT615 616 - If set, the transfer will replace the transfer currently being executed at617 the end of the transfer.618 619 - This is the default behaviour for non-repeated transfers, specifying620 DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference.621 622 - When using repeated transfers, DMA clients will usually need to set the623 DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep624 repeating the last repeated transfer and ignore the new transfers being625 queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was626 stuck on the previous transfer.627 628 - This flag is only supported if the channel reports the DMA_LOAD_EOT629 capability.630 631General Design Notes632====================633 634Most of the DMAEngine drivers you'll see are based on a similar design635that handles the end of transfer interrupts in the handler, but defer636most work to a tasklet, including the start of a new transfer whenever637the previous transfer ended.638 639This is a rather inefficient design though, because the inter-transfer640latency will be not only the interrupt latency, but also the641scheduling latency of the tasklet, which will leave the channel idle642in between, which will slow down the global transfer rate.643 644You should avoid this kind of practice, and instead of electing a new645transfer in your tasklet, move that part to the interrupt handler in646order to have a shorter idle window (that we can't really avoid647anyway).648 649Glossary650========651 652- Burst: A number of consecutive read or write operations that653 can be queued to buffers before being flushed to memory.654 655- Chunk: A contiguous collection of bursts656 657- Transfer: A collection of chunks (be it contiguous or not)658