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1.. SPDX-License-Identifier: GPL-2.02 3=====================4Chrome OS ACPI Device5=====================6 7Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.8The plug and play ID of a Chrome OS ACPI device is GGL0001 and the hardware ID is9GOOG0016. The following ACPI objects are supported:10 11.. flat-table:: Supported ACPI Objects12 :widths: 1 213 :header-rows: 114 15 * - Object16 - Description17 18 * - CHSW19 - Chrome OS switch positions20 21 * - HWID22 - Chrome OS hardware ID23 24 * - FWID25 - Chrome OS firmware version26 27 * - FRID28 - Chrome OS read-only firmware version29 30 * - BINF31 - Chrome OS boot information32 33 * - GPIO34 - Chrome OS GPIO assignments35 36 * - VBNV37 - Chrome OS NVRAM locations38 39 * - VDTA40 - Chrome OS verified boot data41 42 * - FMAP43 - Chrome OS flashmap base address44 45 * - MLST46 - Chrome OS method list47 48CHSW (Chrome OS switch positions)49=================================50This control method returns the switch positions for Chrome OS specific hardware switches.51 52Arguments:53----------54None55 56Result code:57------------58An integer containing the switch positions as bitfields:59 60.. flat-table::61 :widths: 1 262 63 * - 0x0000000264 - Recovery button was pressed when x86 firmware booted.65 66 * - 0x0000000467 - Recovery button was pressed when EC firmware booted. (required if EC EEPROM is68 rewritable; otherwise optional)69 70 * - 0x0000002071 - Developer switch was enabled when x86 firmware booted.72 73 * - 0x0000020074 - Firmware write protection was disabled when x86 firmware booted. (required if75 firmware write protection is controlled through x86 BIOS; otherwise optional)76 77All other bits are reserved and should be set to 0.78 79HWID (Chrome OS hardware ID)80============================81This control method returns the hardware ID for the Chromebook.82 83Arguments:84----------85None86 87Result code:88------------89A null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of90EEPROM.91 92Note that the hardware ID can be up to 256 characters long, including the terminating null.93 94FWID (Chrome OS firmware version)95=================================96This control method returns the firmware version for the rewritable portion of the main97processor firmware.98 99Arguments:100----------101None102 103Result code:104------------105A null-terminated ASCII string containing the complete firmware version for the rewritable106portion of the main processor firmware.107 108FRID (Chrome OS read-only firmware version)109===========================================110This control method returns the firmware version for the read-only portion of the main111processor firmware.112 113Arguments:114----------115None116 117Result code:118------------119A null-terminated ASCII string containing the complete firmware version for the read-only120(bootstrap + recovery ) portion of the main processor firmware.121 122BINF (Chrome OS boot information)123=================================124This control method returns information about the current boot.125 126Arguments:127----------128None129 130Result code:131------------132 133.. code-block::134 135 Package {136 Reserved1137 Reserved2138 Active EC Firmware139 Active Main Firmware Type140 Reserved5141 }142 143.. flat-table::144 :widths: 1 1 2145 :header-rows: 1146 147 * - Field148 - Format149 - Description150 151 * - Reserved1152 - DWORD153 - Set to 256 (0x100). This indicates this field is no longer used.154 155 * - Reserved2156 - DWORD157 - Set to 256 (0x100). This indicates this field is no longer used.158 159 * - Active EC firmware160 - DWORD161 - The EC firmware which was used during boot.162 163 - 0 - Read-only (recovery) firmware164 - 1 - Rewritable firmware.165 166 Set to 0 if EC firmware is always read-only.167 168 * - Active Main Firmware Type169 - DWORD170 - The main firmware type which was used during boot.171 172 - 0 - Recovery173 - 1 - Normal174 - 2 - Developer175 - 3 - netboot (factory installation only)176 177 Other values are reserved.178 179 * - Reserved5180 - DWORD181 - Set to 256 (0x100). This indicates this field is no longer used.182 183GPIO (Chrome OS GPIO assignments)184=================================185This control method returns information about Chrome OS specific GPIO assignments for186Chrome OS hardware, so the kernel can directly control that hardware.187 188Arguments:189----------190None191 192Result code:193------------194.. code-block::195 196 Package {197 Package {198 // First GPIO assignment199 Signal Type //DWORD200 Attributes //DWORD201 Controller Offset //DWORD202 Controller Name //ASCIIZ203 },204 ...205 Package {206 // Last GPIO assignment207 Signal Type //DWORD208 Attributes //DWORD209 Controller Offset //DWORD210 Controller Name //ASCIIZ211 }212 }213 214Where ASCIIZ means a null-terminated ASCII string.215 216.. flat-table::217 :widths: 1 1 2218 :header-rows: 1219 220 * - Field221 - Format222 - Description223 224 * - Signal Type225 - DWORD226 - Type of GPIO signal227 228 - 0x00000001 - Recovery button229 - 0x00000002 - Developer mode switch230 - 0x00000003 - Firmware write protection switch231 - 0x00000100 - Debug header GPIO 0232 - ...233 - 0x000001FF - Debug header GPIO 255234 235 Other values are reserved.236 237 * - Attributes238 - DWORD239 - Signal attributes as bitfields:240 241 - 0x00000001 - Signal is active-high (for button, a GPIO value242 of 1 means the button is pressed; for switches, a GPIO value243 of 1 means the switch is enabled). If this bit is 0, the signal244 is active low. Set to 0 for debug header GPIOs.245 246 * - Controller Offset247 - DWORD248 - GPIO number on the specified controller.249 250 * - Controller Name251 - ASCIIZ252 - Name of the controller for the GPIO.253 Currently supported names:254 "NM10" - Intel NM10 chip255 256VBNV (Chrome OS NVRAM locations)257================================258This control method returns information about the NVRAM (CMOS) locations used to259communicate with the BIOS.260 261Arguments:262----------263None264 265Result code:266------------267.. code-block::268 269 Package {270 NV Storage Block Offset //DWORD271 NV Storage Block Size //DWORD272 }273 274.. flat-table::275 :widths: 1 1 2276 :header-rows: 1277 278 * - Field279 - Format280 - Description281 282 * - NV Storage Block Offset283 - DWORD284 - Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from285 the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of286 clock data).287 288 * - NV Storage Block Size289 - DWORD290 - Size in bytes of the verified boot non-volatile storage block.291 292FMAP (Chrome OS flashmap address)293=================================294This control method returns the physical memory address of the start of the main processor295firmware flashmap.296 297Arguments:298----------299None300 301NoneResult code:302----------------303A DWORD containing the physical memory address of the start of the main processor firmware304flashmap.305 306VDTA (Chrome OS verified boot data)307===================================308This control method returns the verified boot data block shared between the firmware309verification step and the kernel verification step.310 311Arguments:312----------313None314 315Result code:316------------317A buffer containing the verified boot data block.318 319MECK (Management Engine Checksum)320=================================321This control method returns the SHA-1 or SHA-256 hash that is read out of the Management322Engine extended registers during boot. The hash is exported via ACPI so the OS can verify that323the ME firmware has not changed. If Management Engine is not present, or if the firmware was324unable to read the extended registers, this buffer can be zero.325 326Arguments:327----------328None329 330Result code:331------------332A buffer containing the ME hash.333 334MLST (Chrome OS method list)335============================336This control method returns a list of the other control methods supported by the Chrome OS337hardware device.338 339Arguments:340----------341None342 343Result code:344------------345A package containing a list of null-terminated ASCII strings, one for each control method346supported by the Chrome OS hardware device, not including the MLST method itself.347For this version of the specification, the result is:348 349.. code-block::350 351 Package {352 "CHSW",353 "FWID",354 "HWID",355 "FRID",356 "BINF",357 "GPIO",358 "VBNV",359 "FMAP",360 "VDTA",361 "MECK"362 }363