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1===========================2 drm/i915 Intel GFX Driver3===========================4 5The drm/i915 driver supports all (with the exception of some very early6models) integrated GFX chipsets with both Intel display and rendering7blocks. This excludes a set of SoC platforms with an SGX rendering unit,8those have basic support through the gma500 drm driver.9 10Core Driver Infrastructure11==========================12 13This section covers core driver infrastructure used by both the display14and the GEM parts of the driver.15 16Runtime Power Management17------------------------18 19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c20 :doc: runtime pm21 22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c23 :internal:24 25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c26 :internal:27 28Interrupt Handling29------------------30 31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c32 :doc: interrupt handling33 34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init36 37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c38 :functions: intel_runtime_pm_disable_interrupts39 40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c41 :functions: intel_runtime_pm_enable_interrupts42 43Intel GVT-g Guest Support(vGPU)44-------------------------------45 46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c47 :doc: Intel GVT-g guest support48 49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c50 :internal:51 52Intel GVT-g Host Support(vGPU device model)53-------------------------------------------54 55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c56 :doc: Intel GVT-g host support57 58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c59 :internal:60 61Workarounds62-----------63 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c65 :doc: Hardware workarounds66 67Display Hardware Handling68=========================69 70This section covers everything related to the display hardware including71the mode setting infrastructure, plane, sprite and cursor handling and72display, output probing and related topics.73 74Mode Setting Infrastructure75---------------------------76 77The i915 driver is thus far the only DRM driver which doesn't use the78common DRM helper code to implement mode setting sequences. Thus it has79its own tailor-made infrastructure for executing a display configuration80change.81 82Frontbuffer Tracking83--------------------84 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c86 :doc: frontbuffer tracking87 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h89 :internal:90 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c92 :internal:93 94Display FIFO Underrun Reporting95-------------------------------96 97.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c98 :doc: fifo underrun handling99 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c101 :internal:102 103Plane Configuration104-------------------105 106This section covers plane configuration and composition with the primary107plane, sprites, cursors and overlays. This includes the infrastructure108to do atomic vsync'ed updates of all this state and also tightly coupled109topics like watermark setup and computation, framebuffer compression and110panel self refresh.111 112Atomic Plane Helpers113--------------------114 115.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c116 :doc: atomic plane helpers117 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c119 :internal:120 121Asynchronous Page Flip122----------------------123 124.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c125 :doc: asynchronous flip implementation126 127Output Probing128--------------129 130This section covers output probing and related infrastructure like the131hotplug interrupt storm detection and mitigation code. Note that the132i915 driver still uses most of the common DRM helper code for output133probing, so those sections fully apply.134 135Hotplug136-------137 138.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c139 :doc: Hotplug140 141.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c142 :internal:143 144High Definition Audio145---------------------146 147.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c148 :doc: High Definition Audio over HDMI and Display Port149 150.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c151 :internal:152 153.. kernel-doc:: include/drm/intel/i915_component.h154 :internal:155 156Intel HDMI LPE Audio Support157----------------------------158 159.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c160 :doc: LPE Audio integration for HDMI or DP playback161 162.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c163 :internal:164 165Panel Self Refresh PSR (PSR/SRD)166--------------------------------167 168.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c169 :doc: Panel Self Refresh (PSR/SRD)170 171.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c172 :internal:173 174Frame Buffer Compression (FBC)175------------------------------176 177.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c178 :doc: Frame Buffer Compression (FBC)179 180.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c181 :internal:182 183Display Refresh Rate Switching (DRRS)184-------------------------------------185 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c187 :doc: Display Refresh Rate Switching (DRRS)188 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c190 :internal:191 192DPIO193----194 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c196 :doc: DPIO197 198DMC Firmware Support199--------------------200 201.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c202 :doc: DMC Firmware Support203 204.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c205 :internal:206 207DMC wakelock support208--------------------209 210.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c211 :doc: DMC wakelock support212 213Video BIOS Table (VBT)214----------------------215 216.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c217 :doc: Video BIOS Table (VBT)218 219.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c220 :internal:221 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h223 :internal:224 225Display clocks226--------------227 228.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c229 :doc: CDCLK / RAWCLK230 231.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c232 :internal:233 234Display PLLs235------------236 237.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c238 :doc: Display PLLs239 240.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c241 :internal:242 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h244 :internal:245 246Display State Buffer247--------------------248 249.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c250 :doc: DSB251 252.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c253 :internal:254 255GT Programming256==============257 258Multicast/Replicated (MCR) Registers259------------------------------------260 261.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c262 :doc: GT Multicast/Replicated (MCR) Register Support263 264.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c265 :internal:266 267Memory Management and Command Submission268========================================269 270This sections covers all things related to the GEM implementation in the271i915 driver.272 273Intel GPU Basics274----------------275 276An Intel GPU has multiple engines. There are several engine types:277 278- Render Command Streamer (RCS). An engine for rendering 3D and279 performing compute.280- Blitting Command Streamer (BCS). An engine for performing blitting and/or281 copying operations.282- Video Command Streamer. An engine used for video encoding and decoding. Also283 sometimes called 'BSD' in hardware documentation.284- Video Enhancement Command Streamer (VECS). An engine for video enhancement.285 Also sometimes called 'VEBOX' in hardware documentation.286- Compute Command Streamer (CCS). An engine that has access to the media and287 GPGPU pipelines, but not the 3D pipeline.288- Graphics Security Controller (GSCCS). A dedicated engine for internal289 communication with GSC controller on security related tasks like290 High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP),291 and HuC firmware authentication.292 293The Intel GPU family is a family of integrated GPU's using Unified294Memory Access. For having the GPU "do work", user space will feed the295GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`296or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will297instruct the GPU to perform work (for example rendering) and that work298needs memory from which to read and memory to which to write. All memory299is encapsulated within GEM buffer objects (usually created with the ioctl300`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU301to create will also list all GEM buffer objects that the batchbuffer reads302and/or writes. For implementation details of memory management see303`GEM BO Management Implementation Details`_.304 305The i915 driver allows user space to create a context via the ioctl306`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit307integer. Such a context should be viewed by user-space as -loosely-308analogous to the idea of a CPU process of an operating system. The i915309driver guarantees that commands issued to a fixed context are to be310executed so that writes of a previously issued command are seen by311reads of following commands. Actions issued between different contexts312(even if from the same file descriptor) are NOT given that guarantee313and the only way to synchronize across contexts (even from the same314file descriptor) is through the use of fences. At least as far back as315Gen4, also have that a context carries with it a GPU HW context;316the HW context is essentially (most of at least) the state of a GPU.317In addition to the ordering guarantees, the kernel will restore GPU318state via HW context when commands are issued to a context, this saves319user space the need to restore (most of at least) the GPU state at the320start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer321work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)322to identify what context to use with the command.323 324The GPU has its own memory management and address space. The kernel325driver maintains the memory translation table for the GPU. For older326GPUs (i.e. those before Gen8), there is a single global such translation327table, a global Graphics Translation Table (GTT). For newer generation328GPUs each context has its own translation table, called Per-Process329Graphics Translation Table (PPGTT). Of important note, is that although330PPGTT is named per-process it is actually per context. When user space331submits a batchbuffer, the kernel walks the list of GEM buffer objects332used by the batchbuffer and guarantees that not only is the memory of333each such GEM buffer object resident but it is also present in the334(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,335then it is given an address. Two consequences of this are: the kernel336needs to edit the batchbuffer submitted to write the correct value of337the GPU address when a GEM BO is assigned a GPU address and the kernel338might evict a different GEM BO from the (PP)GTT to make address room339for another GEM BO. Consequently, the ioctls submitting a batchbuffer340for execution also include a list of all locations within buffers that341refer to GPU-addresses so that the kernel can edit the buffer correctly.342This process is dubbed relocation.343 344Locking Guidelines345------------------346 347.. note::348 This is a description of how the locking should be after349 refactoring is done. Does not necessarily reflect what the locking350 looks like while WIP.351 352#. All locking rules and interface contracts with cross-driver interfaces353 (dma-buf, dma_fence) need to be followed.354 355#. No struct_mutex anywhere in the code356 357#. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx358 is to be hoisted at highest level and passed down within i915_gem_ctx359 in the call chain360 361#. While holding lru/memory manager (buddy, drm_mm, whatever) locks362 system memory allocations are not allowed363 364 * Enforce this by priming lockdep (with fs_reclaim). If we365 allocate memory while holding these looks we get a rehash366 of the shrinker vs. struct_mutex saga, and that would be367 real bad.368 369#. Do not nest different lru/memory manager locks within each other.370 Take them in turn to update memory allocations, relying on the object’s371 dma_resv ww_mutex to serialize against other operations.372 373#. The suggestion for lru/memory managers locks is that they are small374 enough to be spinlocks.375 376#. All features need to come with exhaustive kernel selftests and/or377 IGT tests when appropriate378 379#. All LMEM uAPI paths need to be fully restartable (_interruptible()380 for all locks/waits/sleeps)381 382 * Error handling validation through signal injection.383 Still the best strategy we have for validating GEM uAPI384 corner cases.385 Must be excessively used in the IGT, and we need to check386 that we really have full path coverage of all error cases.387 388 * -EDEADLK handling with ww_mutex389 390GEM BO Management Implementation Details391----------------------------------------392 393.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h394 :doc: Virtual Memory Address395 396Buffer Object Eviction397----------------------398 399This section documents the interface functions for evicting buffer400objects to make space available in the virtual gpu address spaces. Note401that this is mostly orthogonal to shrinking buffer objects caches, which402has the goal to make main memory (shared with the gpu through the403unified memory architecture) available.404 405.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c406 :internal:407 408Buffer Object Memory Shrinking409------------------------------410 411This section documents the interface function for shrinking memory usage412of buffer object caches. Shrinking is used to make main memory413available. Note that this is mostly orthogonal to evicting buffer414objects, which has the goal to make space in gpu virtual address spaces.415 416.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c417 :internal:418 419Batchbuffer Parsing420-------------------421 422.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c423 :doc: batch buffer command parser424 425.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c426 :internal:427 428User Batchbuffer Execution429--------------------------430 431.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h432 433.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c434 :doc: User command execution435 436Scheduling437----------438.. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h439 :functions: i915_sched_engine440 441Logical Rings, Logical Ring Contexts and Execlists442--------------------------------------------------443 444.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c445 :doc: Logical Rings, Logical Ring Contexts and Execlists446 447Global GTT views448----------------449 450.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h451 :doc: Global GTT views452 453.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c454 :internal:455 456GTT Fences and Swizzling457------------------------458 459.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c460 :internal:461 462Global GTT Fence Handling463~~~~~~~~~~~~~~~~~~~~~~~~~464 465.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c466 :doc: fence register handling467 468Hardware Tiling and Swizzling Details469~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~470 471.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c472 :doc: tiling swizzling details473 474Object Tiling IOCTLs475--------------------476 477.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c478 :internal:479 480.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c481 :doc: buffer object tiling482 483Protected Objects484-----------------485 486.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c487 :doc: PXP488 489.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h490 491Microcontrollers492================493 494Starting from gen9, three microcontrollers are available on the HW: the495graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the496display microcontroller (DMC). The driver is responsible for loading the497firmwares on the microcontrollers; the GuC and HuC firmwares are transferred498to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.499 500WOPCM501-----502 503WOPCM Layout504~~~~~~~~~~~~505 506.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_wopcm.c507 :doc: WOPCM Layout508 509GuC510---511 512.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c513 :doc: GuC514 515.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h516 517GuC Firmware Layout518~~~~~~~~~~~~~~~~~~~519 520.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h521 :doc: Firmware Layout522 523GuC Memory Management524~~~~~~~~~~~~~~~~~~~~~525 526.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c527 :doc: GuC Memory Management528.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c529 :functions: intel_guc_allocate_vma530 531 532GuC-specific firmware loader533~~~~~~~~~~~~~~~~~~~~~~~~~~~~534 535.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c536 :internal:537 538GuC-based command submission539~~~~~~~~~~~~~~~~~~~~~~~~~~~~540 541.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c542 :doc: GuC-based command submission543 544GuC ABI545~~~~~~~~~~~~~~~~~~~~~~~~~~~~546 547.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h548.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h549.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h550.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h551.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h552 553HuC554---555.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c556 :doc: HuC557.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c558 :functions: intel_huc_auth559 560HuC Memory Management561~~~~~~~~~~~~~~~~~~~~~562 563.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c564 :doc: HuC Memory Management565 566HuC Firmware Layout567~~~~~~~~~~~~~~~~~~~568The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_569 570DMC571---572See `DMC Firmware Support`_573 574Tracing575=======576 577This sections covers all things related to the tracepoints implemented578in the i915 driver.579 580i915_ppgtt_create and i915_ppgtt_release581----------------------------------------582 583.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h584 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints585 586i915_context_create and i915_context_free587-----------------------------------------588 589.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h590 :doc: i915_context_create and i915_context_free tracepoints591 592Perf593====594 595Overview596--------597.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c598 :doc: i915 Perf Overview599 600Comparison with Core Perf601-------------------------602.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c603 :doc: i915 Perf History and Comparison with Core Perf604 605i915 Driver Entry Points606------------------------607 608This section covers the entrypoints exported outside of i915_perf.c to609integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.610 611.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c612 :functions: i915_perf_init613.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c614 :functions: i915_perf_fini615.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c616 :functions: i915_perf_register617.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c618 :functions: i915_perf_unregister619.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c620 :functions: i915_perf_open_ioctl621.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c622 :functions: i915_perf_release623.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c624 :functions: i915_perf_add_config_ioctl625.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c626 :functions: i915_perf_remove_config_ioctl627 628i915 Perf Stream629----------------630 631This section covers the stream-semantics-agnostic structures and functions632for representing an i915 perf stream FD and associated file operations.633 634.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h635 :functions: i915_perf_stream636.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h637 :functions: i915_perf_stream_ops638 639.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c640 :functions: read_properties_unlocked641.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c642 :functions: i915_perf_open_ioctl_locked643.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c644 :functions: i915_perf_destroy_locked645.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c646 :functions: i915_perf_read647.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c648 :functions: i915_perf_ioctl649.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c650 :functions: i915_perf_enable_locked651.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c652 :functions: i915_perf_disable_locked653.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c654 :functions: i915_perf_poll655.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c656 :functions: i915_perf_poll_locked657 658i915 Perf Observation Architecture Stream659-----------------------------------------660 661.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h662 :functions: i915_oa_ops663 664.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c665 :functions: i915_oa_stream_init666.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c667 :functions: i915_oa_read668.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c669 :functions: i915_oa_stream_enable670.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c671 :functions: i915_oa_stream_disable672.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c673 :functions: i915_oa_wait_unlocked674.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c675 :functions: i915_oa_poll_wait676 677Other i915 Perf Internals678-------------------------679 680This section simply includes all other currently documented i915 perf internals,681in no particular order, but may include some more minor utilities or platform682specific details than found in the more high-level sections.683 684.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c685 :internal:686 :no-identifiers:687 i915_perf_init688 i915_perf_fini689 i915_perf_register690 i915_perf_unregister691 i915_perf_open_ioctl692 i915_perf_release693 i915_perf_add_config_ioctl694 i915_perf_remove_config_ioctl695 read_properties_unlocked696 i915_perf_open_ioctl_locked697 i915_perf_destroy_locked698 i915_perf_read i915_perf_ioctl699 i915_perf_enable_locked700 i915_perf_disable_locked701 i915_perf_poll i915_perf_poll_locked702 i915_oa_stream_init i915_oa_read703 i915_oa_stream_enable704 i915_oa_stream_disable705 i915_oa_wait_unlocked706 i915_oa_poll_wait707 708Style709=====710 711The drm/i915 driver codebase has some style rules in addition to (and, in some712cases, deviating from) the kernel coding style.713 714Register macro definition style715-------------------------------716 717The style guide for ``i915_reg.h``.718 719.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h720 :doc: The i915 register macro definition style guide721 722.. _i915-usage-stats:723 724i915 DRM client usage stats implementation725==========================================726 727The drm/i915 driver implements the DRM client usage stats specification as728documented in :ref:`drm-client-usage-stats`.729 730Example of the output showing the implemented key value pairs and entirety of731the currently possible format options:732 733::734 735 pos: 0736 flags: 0100002737 mnt_id: 21738 drm-driver: i915739 drm-pdev: 0000:00:02.0740 drm-client-id: 7741 drm-engine-render: 9288864723 ns742 drm-engine-copy: 2035071108 ns743 drm-engine-video: 0 ns744 drm-engine-capacity-video: 2745 drm-engine-video-enhance: 0 ns746 747Possible `drm-engine-` key names are: `render`, `copy`, `video` and748`video-enhance`.749