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1 ============================2 LINUX KERNEL MEMORY BARRIERS3 ============================4 5By: David Howells <dhowells@redhat.com>6 Paul E. McKenney <paulmck@linux.ibm.com>7 Will Deacon <will.deacon@arm.com>8 Peter Zijlstra <peterz@infradead.org>9 10==========11DISCLAIMER12==========13 14This document is not a specification; it is intentionally (for the sake of15brevity) and unintentionally (due to being human) incomplete. This document is16meant as a guide to using the various memory barriers provided by Linux, but17in case of any doubt (and there are many) please ask. Some doubts may be18resolved by referring to the formal memory consistency model and related19documentation at tools/memory-model/. Nevertheless, even this memory20model should be viewed as the collective opinion of its maintainers rather21than as an infallible oracle.22 23To repeat, this document is not a specification of what Linux expects from24hardware.25 26The purpose of this document is twofold:27 28 (1) to specify the minimum functionality that one can rely on for any29 particular barrier, and30 31 (2) to provide a guide as to how to use the barriers that are available.32 33Note that an architecture can provide more than the minimum requirement34for any particular barrier, but if the architecture provides less than35that, that architecture is incorrect.36 37Note also that it is possible that a barrier may be a no-op for an38architecture because the way that arch works renders an explicit barrier39unnecessary in that case.40 41 42========43CONTENTS44========45 46 (*) Abstract memory access model.47 48 - Device operations.49 - Guarantees.50 51 (*) What are memory barriers?52 53 - Varieties of memory barrier.54 - What may not be assumed about memory barriers?55 - Address-dependency barriers (historical).56 - Control dependencies.57 - SMP barrier pairing.58 - Examples of memory barrier sequences.59 - Read memory barriers vs load speculation.60 - Multicopy atomicity.61 62 (*) Explicit kernel barriers.63 64 - Compiler barrier.65 - CPU memory barriers.66 67 (*) Implicit kernel memory barriers.68 69 - Lock acquisition functions.70 - Interrupt disabling functions.71 - Sleep and wake-up functions.72 - Miscellaneous functions.73 74 (*) Inter-CPU acquiring barrier effects.75 76 - Acquires vs memory accesses.77 78 (*) Where are memory barriers needed?79 80 - Interprocessor interaction.81 - Atomic operations.82 - Accessing devices.83 - Interrupts.84 85 (*) Kernel I/O barrier effects.86 87 (*) Assumed minimum execution ordering model.88 89 (*) The effects of the cpu cache.90 91 - Cache coherency vs DMA.92 - Cache coherency vs MMIO.93 94 (*) The things CPUs get up to.95 96 - And then there's the Alpha.97 - Virtual Machine Guests.98 99 (*) Example uses.100 101 - Circular buffers.102 103 (*) References.104 105 106============================107ABSTRACT MEMORY ACCESS MODEL108============================109 110Consider the following abstract model of the system:111 112 : :113 : :114 : :115 +-------+ : +--------+ : +-------+116 | | : | | : | |117 | | : | | : | |118 | CPU 1 |<----->| Memory |<----->| CPU 2 |119 | | : | | : | |120 | | : | | : | |121 +-------+ : +--------+ : +-------+122 ^ : ^ : ^123 | : | : |124 | : | : |125 | : v : |126 | : +--------+ : |127 | : | | : |128 | : | | : |129 +---------->| Device |<----------+130 : | | :131 : | | :132 : +--------+ :133 : :134 135Each CPU executes a program that generates memory access operations. In the136abstract CPU, memory operation ordering is very relaxed, and a CPU may actually137perform the memory operations in any order it likes, provided program causality138appears to be maintained. Similarly, the compiler may also arrange the139instructions it emits in any order it likes, provided it doesn't affect the140apparent operation of the program.141 142So in the above diagram, the effects of the memory operations performed by a143CPU are perceived by the rest of the system as the operations cross the144interface between the CPU and rest of the system (the dotted lines).145 146 147For example, consider the following sequence of events:148 149 CPU 1 CPU 2150 =============== ===============151 { A == 1; B == 2 }152 A = 3; x = B;153 B = 4; y = A;154 155The set of accesses as seen by the memory system in the middle can be arranged156in 24 different combinations:157 158 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4159 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3160 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4161 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4162 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3163 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4164 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4165 STORE B=4, ...166 ...167 168and can thus result in four different combinations of values:169 170 x == 2, y == 1171 x == 2, y == 3172 x == 4, y == 1173 x == 4, y == 3174 175 176Furthermore, the stores committed by a CPU to the memory system may not be177perceived by the loads made by another CPU in the same order as the stores were178committed.179 180 181As a further example, consider this sequence of events:182 183 CPU 1 CPU 2184 =============== ===============185 { A == 1, B == 2, C == 3, P == &A, Q == &C }186 B = 4; Q = P;187 P = &B; D = *Q;188 189There is an obvious address dependency here, as the value loaded into D depends190on the address retrieved from P by CPU 2. At the end of the sequence, any of191the following results are possible:192 193 (Q == &A) and (D == 1)194 (Q == &B) and (D == 2)195 (Q == &B) and (D == 4)196 197Note that CPU 2 will never try and load C into D because the CPU will load P198into Q before issuing the load of *Q.199 200 201DEVICE OPERATIONS202-----------------203 204Some devices present their control interfaces as collections of memory205locations, but the order in which the control registers are accessed is very206important. For instance, imagine an ethernet card with a set of internal207registers that are accessed through an address port register (A) and a data208port register (D). To read internal register 5, the following code might then209be used:210 211 *A = 5;212 x = *D;213 214but this might show up as either of the following two sequences:215 216 STORE *A = 5, x = LOAD *D217 x = LOAD *D, STORE *A = 5218 219the second of which will almost certainly result in a malfunction, since it set220the address _after_ attempting to read the register.221 222 223GUARANTEES224----------225 226There are some minimal guarantees that may be expected of a CPU:227 228 (*) On any given CPU, dependent memory accesses will be issued in order, with229 respect to itself. This means that for:230 231 Q = READ_ONCE(P); D = READ_ONCE(*Q);232 233 the CPU will issue the following memory operations:234 235 Q = LOAD P, D = LOAD *Q236 237 and always in that order. However, on DEC Alpha, READ_ONCE() also238 emits a memory-barrier instruction, so that a DEC Alpha CPU will239 instead issue the following memory operations:240 241 Q = LOAD P, MEMORY_BARRIER, D = LOAD *Q, MEMORY_BARRIER242 243 Whether on DEC Alpha or not, the READ_ONCE() also prevents compiler244 mischief.245 246 (*) Overlapping loads and stores within a particular CPU will appear to be247 ordered within that CPU. This means that for:248 249 a = READ_ONCE(*X); WRITE_ONCE(*X, b);250 251 the CPU will only issue the following sequence of memory operations:252 253 a = LOAD *X, STORE *X = b254 255 And for:256 257 WRITE_ONCE(*X, c); d = READ_ONCE(*X);258 259 the CPU will only issue:260 261 STORE *X = c, d = LOAD *X262 263 (Loads and stores overlap if they are targeted at overlapping pieces of264 memory).265 266And there are a number of things that _must_ or _must_not_ be assumed:267 268 (*) It _must_not_ be assumed that the compiler will do what you want269 with memory references that are not protected by READ_ONCE() and270 WRITE_ONCE(). Without them, the compiler is within its rights to271 do all sorts of "creative" transformations, which are covered in272 the COMPILER BARRIER section.273 274 (*) It _must_not_ be assumed that independent loads and stores will be issued275 in the order given. This means that for:276 277 X = *A; Y = *B; *D = Z;278 279 we may get any of the following sequences:280 281 X = LOAD *A, Y = LOAD *B, STORE *D = Z282 X = LOAD *A, STORE *D = Z, Y = LOAD *B283 Y = LOAD *B, X = LOAD *A, STORE *D = Z284 Y = LOAD *B, STORE *D = Z, X = LOAD *A285 STORE *D = Z, X = LOAD *A, Y = LOAD *B286 STORE *D = Z, Y = LOAD *B, X = LOAD *A287 288 (*) It _must_ be assumed that overlapping memory accesses may be merged or289 discarded. This means that for:290 291 X = *A; Y = *(A + 4);292 293 we may get any one of the following sequences:294 295 X = LOAD *A; Y = LOAD *(A + 4);296 Y = LOAD *(A + 4); X = LOAD *A;297 {X, Y} = LOAD {*A, *(A + 4) };298 299 And for:300 301 *A = X; *(A + 4) = Y;302 303 we may get any of:304 305 STORE *A = X; STORE *(A + 4) = Y;306 STORE *(A + 4) = Y; STORE *A = X;307 STORE {*A, *(A + 4) } = {X, Y};308 309And there are anti-guarantees:310 311 (*) These guarantees do not apply to bitfields, because compilers often312 generate code to modify these using non-atomic read-modify-write313 sequences. Do not attempt to use bitfields to synchronize parallel314 algorithms.315 316 (*) Even in cases where bitfields are protected by locks, all fields317 in a given bitfield must be protected by one lock. If two fields318 in a given bitfield are protected by different locks, the compiler's319 non-atomic read-modify-write sequences can cause an update to one320 field to corrupt the value of an adjacent field.321 322 (*) These guarantees apply only to properly aligned and sized scalar323 variables. "Properly sized" currently means variables that are324 the same size as "char", "short", "int" and "long". "Properly325 aligned" means the natural alignment, thus no constraints for326 "char", two-byte alignment for "short", four-byte alignment for327 "int", and either four-byte or eight-byte alignment for "long",328 on 32-bit and 64-bit systems, respectively. Note that these329 guarantees were introduced into the C11 standard, so beware when330 using older pre-C11 compilers (for example, gcc 4.6). The portion331 of the standard containing this guarantee is Section 3.14, which332 defines "memory location" as follows:333 334 memory location335 either an object of scalar type, or a maximal sequence336 of adjacent bit-fields all having nonzero width337 338 NOTE 1: Two threads of execution can update and access339 separate memory locations without interfering with340 each other.341 342 NOTE 2: A bit-field and an adjacent non-bit-field member343 are in separate memory locations. The same applies344 to two bit-fields, if one is declared inside a nested345 structure declaration and the other is not, or if the two346 are separated by a zero-length bit-field declaration,347 or if they are separated by a non-bit-field member348 declaration. It is not safe to concurrently update two349 bit-fields in the same structure if all members declared350 between them are also bit-fields, no matter what the351 sizes of those intervening bit-fields happen to be.352 353 354=========================355WHAT ARE MEMORY BARRIERS?356=========================357 358As can be seen above, independent memory operations are effectively performed359in random order, but this can be a problem for CPU-CPU interaction and for I/O.360What is required is some way of intervening to instruct the compiler and the361CPU to restrict the order.362 363Memory barriers are such interventions. They impose a perceived partial364ordering over the memory operations on either side of the barrier.365 366Such enforcement is important because the CPUs and other devices in a system367can use a variety of tricks to improve performance, including reordering,368deferral and combination of memory operations; speculative loads; speculative369branch prediction and various types of caching. Memory barriers are used to370override or suppress these tricks, allowing the code to sanely control the371interaction of multiple CPUs and/or devices.372 373 374VARIETIES OF MEMORY BARRIER375---------------------------376 377Memory barriers come in four basic varieties:378 379 (1) Write (or store) memory barriers.380 381 A write memory barrier gives a guarantee that all the STORE operations382 specified before the barrier will appear to happen before all the STORE383 operations specified after the barrier with respect to the other384 components of the system.385 386 A write barrier is a partial ordering on stores only; it is not required387 to have any effect on loads.388 389 A CPU can be viewed as committing a sequence of store operations to the390 memory system as time progresses. All stores _before_ a write barrier391 will occur _before_ all the stores after the write barrier.392 393 [!] Note that write barriers should normally be paired with read or394 address-dependency barriers; see the "SMP barrier pairing" subsection.395 396 397 (2) Address-dependency barriers (historical).398 [!] This section is marked as HISTORICAL: it covers the long-obsolete399 smp_read_barrier_depends() macro, the semantics of which are now400 implicit in all marked accesses. For more up-to-date information,401 including how compiler transformations can sometimes break address402 dependencies, see Documentation/RCU/rcu_dereference.rst.403 404 An address-dependency barrier is a weaker form of read barrier. In the405 case where two loads are performed such that the second depends on the406 result of the first (eg: the first load retrieves the address to which407 the second load will be directed), an address-dependency barrier would408 be required to make sure that the target of the second load is updated409 after the address obtained by the first load is accessed.410 411 An address-dependency barrier is a partial ordering on interdependent412 loads only; it is not required to have any effect on stores, independent413 loads or overlapping loads.414 415 As mentioned in (1), the other CPUs in the system can be viewed as416 committing sequences of stores to the memory system that the CPU being417 considered can then perceive. An address-dependency barrier issued by418 the CPU under consideration guarantees that for any load preceding it,419 if that load touches one of a sequence of stores from another CPU, then420 by the time the barrier completes, the effects of all the stores prior to421 that touched by the load will be perceptible to any loads issued after422 the address-dependency barrier.423 424 See the "Examples of memory barrier sequences" subsection for diagrams425 showing the ordering constraints.426 427 [!] Note that the first load really has to have an _address_ dependency and428 not a control dependency. If the address for the second load is dependent429 on the first load, but the dependency is through a conditional rather than430 actually loading the address itself, then it's a _control_ dependency and431 a full read barrier or better is required. See the "Control dependencies"432 subsection for more information.433 434 [!] Note that address-dependency barriers should normally be paired with435 write barriers; see the "SMP barrier pairing" subsection.436 437 [!] Kernel release v5.9 removed kernel APIs for explicit address-438 dependency barriers. Nowadays, APIs for marking loads from shared439 variables such as READ_ONCE() and rcu_dereference() provide implicit440 address-dependency barriers.441 442 (3) Read (or load) memory barriers.443 444 A read barrier is an address-dependency barrier plus a guarantee that all445 the LOAD operations specified before the barrier will appear to happen446 before all the LOAD operations specified after the barrier with respect to447 the other components of the system.448 449 A read barrier is a partial ordering on loads only; it is not required to450 have any effect on stores.451 452 Read memory barriers imply address-dependency barriers, and so can453 substitute for them.454 455 [!] Note that read barriers should normally be paired with write barriers;456 see the "SMP barrier pairing" subsection.457 458 459 (4) General memory barriers.460 461 A general memory barrier gives a guarantee that all the LOAD and STORE462 operations specified before the barrier will appear to happen before all463 the LOAD and STORE operations specified after the barrier with respect to464 the other components of the system.465 466 A general memory barrier is a partial ordering over both loads and stores.467 468 General memory barriers imply both read and write memory barriers, and so469 can substitute for either.470 471 472And a couple of implicit varieties:473 474 (5) ACQUIRE operations.475 476 This acts as a one-way permeable barrier. It guarantees that all memory477 operations after the ACQUIRE operation will appear to happen after the478 ACQUIRE operation with respect to the other components of the system.479 ACQUIRE operations include LOCK operations and both smp_load_acquire()480 and smp_cond_load_acquire() operations.481 482 Memory operations that occur before an ACQUIRE operation may appear to483 happen after it completes.484 485 An ACQUIRE operation should almost always be paired with a RELEASE486 operation.487 488 489 (6) RELEASE operations.490 491 This also acts as a one-way permeable barrier. It guarantees that all492 memory operations before the RELEASE operation will appear to happen493 before the RELEASE operation with respect to the other components of the494 system. RELEASE operations include UNLOCK operations and495 smp_store_release() operations.496 497 Memory operations that occur after a RELEASE operation may appear to498 happen before it completes.499 500 The use of ACQUIRE and RELEASE operations generally precludes the need501 for other sorts of memory barrier. In addition, a RELEASE+ACQUIRE pair is502 -not- guaranteed to act as a full memory barrier. However, after an503 ACQUIRE on a given variable, all memory accesses preceding any prior504 RELEASE on that same variable are guaranteed to be visible. In other505 words, within a given variable's critical section, all accesses of all506 previous critical sections for that variable are guaranteed to have507 completed.508 509 This means that ACQUIRE acts as a minimal "acquire" operation and510 RELEASE acts as a minimal "release" operation.511 512A subset of the atomic operations described in atomic_t.txt have ACQUIRE and513RELEASE variants in addition to fully-ordered and relaxed (no barrier514semantics) definitions. For compound atomics performing both a load and a515store, ACQUIRE semantics apply only to the load and RELEASE semantics apply516only to the store portion of the operation.517 518Memory barriers are only required where there's a possibility of interaction519between two CPUs or between a CPU and a device. If it can be guaranteed that520there won't be any such interaction in any particular piece of code, then521memory barriers are unnecessary in that piece of code.522 523 524Note that these are the _minimum_ guarantees. Different architectures may give525more substantial guarantees, but they may _not_ be relied upon outside of arch526specific code.527 528 529WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?530----------------------------------------------531 532There are certain things that the Linux kernel memory barriers do not guarantee:533 534 (*) There is no guarantee that any of the memory accesses specified before a535 memory barrier will be _complete_ by the completion of a memory barrier536 instruction; the barrier can be considered to draw a line in that CPU's537 access queue that accesses of the appropriate type may not cross.538 539 (*) There is no guarantee that issuing a memory barrier on one CPU will have540 any direct effect on another CPU or any other hardware in the system. The541 indirect effect will be the order in which the second CPU sees the effects542 of the first CPU's accesses occur, but see the next point:543 544 (*) There is no guarantee that a CPU will see the correct order of effects545 from a second CPU's accesses, even _if_ the second CPU uses a memory546 barrier, unless the first CPU _also_ uses a matching memory barrier (see547 the subsection on "SMP Barrier Pairing").548 549 (*) There is no guarantee that some intervening piece of off-the-CPU550 hardware[*] will not reorder the memory accesses. CPU cache coherency551 mechanisms should propagate the indirect effects of a memory barrier552 between CPUs, but might not do so in order.553 554 [*] For information on bus mastering DMA and coherency please read:555 556 Documentation/driver-api/pci/pci.rst557 Documentation/core-api/dma-api-howto.rst558 Documentation/core-api/dma-api.rst559 560 561ADDRESS-DEPENDENCY BARRIERS (HISTORICAL)562----------------------------------------563[!] This section is marked as HISTORICAL: it covers the long-obsolete564smp_read_barrier_depends() macro, the semantics of which are now implicit565in all marked accesses. For more up-to-date information, including566how compiler transformations can sometimes break address dependencies,567see Documentation/RCU/rcu_dereference.rst.568 569As of v4.15 of the Linux kernel, an smp_mb() was added to READ_ONCE() for570DEC Alpha, which means that about the only people who need to pay attention571to this section are those working on DEC Alpha architecture-specific code572and those working on READ_ONCE() itself. For those who need it, and for573those who are interested in the history, here is the story of574address-dependency barriers.575 576[!] While address dependencies are observed in both load-to-load and577load-to-store relations, address-dependency barriers are not necessary578for load-to-store situations.579 580The requirement of address-dependency barriers is a little subtle, and581it's not always obvious that they're needed. To illustrate, consider the582following sequence of events:583 584 CPU 1 CPU 2585 =============== ===============586 { A == 1, B == 2, C == 3, P == &A, Q == &C }587 B = 4;588 <write barrier>589 WRITE_ONCE(P, &B);590 Q = READ_ONCE_OLD(P);591 D = *Q;592 593[!] READ_ONCE_OLD() corresponds to READ_ONCE() of pre-4.15 kernel, which594doesn't imply an address-dependency barrier.595 596There's a clear address dependency here, and it would seem that by the end of597the sequence, Q must be either &A or &B, and that:598 599 (Q == &A) implies (D == 1)600 (Q == &B) implies (D == 4)601 602But! CPU 2's perception of P may be updated _before_ its perception of B, thus603leading to the following situation:604 605 (Q == &B) and (D == 2) ????606 607While this may seem like a failure of coherency or causality maintenance, it608isn't, and this behaviour can be observed on certain real CPUs (such as the DEC609Alpha).610 611To deal with this, READ_ONCE() provides an implicit address-dependency barrier612since kernel release v4.15:613 614 CPU 1 CPU 2615 =============== ===============616 { A == 1, B == 2, C == 3, P == &A, Q == &C }617 B = 4;618 <write barrier>619 WRITE_ONCE(P, &B);620 Q = READ_ONCE(P);621 <implicit address-dependency barrier>622 D = *Q;623 624This enforces the occurrence of one of the two implications, and prevents the625third possibility from arising.626 627 628[!] Note that this extremely counterintuitive situation arises most easily on629machines with split caches, so that, for example, one cache bank processes630even-numbered cache lines and the other bank processes odd-numbered cache631lines. The pointer P might be stored in an odd-numbered cache line, and the632variable B might be stored in an even-numbered cache line. Then, if the633even-numbered bank of the reading CPU's cache is extremely busy while the634odd-numbered bank is idle, one can see the new value of the pointer P (&B),635but the old value of the variable B (2).636 637 638An address-dependency barrier is not required to order dependent writes639because the CPUs that the Linux kernel supports don't do writes until they640are certain (1) that the write will actually happen, (2) of the location of641the write, and (3) of the value to be written.642But please carefully read the "CONTROL DEPENDENCIES" section and the643Documentation/RCU/rcu_dereference.rst file: The compiler can and does break644dependencies in a great many highly creative ways.645 646 CPU 1 CPU 2647 =============== ===============648 { A == 1, B == 2, C = 3, P == &A, Q == &C }649 B = 4;650 <write barrier>651 WRITE_ONCE(P, &B);652 Q = READ_ONCE_OLD(P);653 WRITE_ONCE(*Q, 5);654 655Therefore, no address-dependency barrier is required to order the read into656Q with the store into *Q. In other words, this outcome is prohibited,657even without an implicit address-dependency barrier of modern READ_ONCE():658 659 (Q == &B) && (B == 4)660 661Please note that this pattern should be rare. After all, the whole point662of dependency ordering is to -prevent- writes to the data structure, along663with the expensive cache misses associated with those writes. This pattern664can be used to record rare error conditions and the like, and the CPUs'665naturally occurring ordering prevents such records from being lost.666 667 668Note well that the ordering provided by an address dependency is local to669the CPU containing it. See the section on "Multicopy atomicity" for670more information.671 672 673The address-dependency barrier is very important to the RCU system,674for example. See rcu_assign_pointer() and rcu_dereference() in675include/linux/rcupdate.h. This permits the current target of an RCU'd676pointer to be replaced with a new modified target, without the replacement677target appearing to be incompletely initialised.678 679 680CONTROL DEPENDENCIES681--------------------682 683Control dependencies can be a bit tricky because current compilers do684not understand them. The purpose of this section is to help you prevent685the compiler's ignorance from breaking your code.686 687A load-load control dependency requires a full read memory barrier, not688simply an (implicit) address-dependency barrier to make it work correctly.689Consider the following bit of code:690 691 q = READ_ONCE(a);692 <implicit address-dependency barrier>693 if (q) {694 /* BUG: No address dependency!!! */695 p = READ_ONCE(b);696 }697 698This will not have the desired effect because there is no actual address699dependency, but rather a control dependency that the CPU may short-circuit700by attempting to predict the outcome in advance, so that other CPUs see701the load from b as having happened before the load from a. In such a case702what's actually required is:703 704 q = READ_ONCE(a);705 if (q) {706 <read barrier>707 p = READ_ONCE(b);708 }709 710However, stores are not speculated. This means that ordering -is- provided711for load-store control dependencies, as in the following example:712 713 q = READ_ONCE(a);714 if (q) {715 WRITE_ONCE(b, 1);716 }717 718Control dependencies pair normally with other types of barriers.719That said, please note that neither READ_ONCE() nor WRITE_ONCE()720are optional! Without the READ_ONCE(), the compiler might combine the721load from 'a' with other loads from 'a'. Without the WRITE_ONCE(),722the compiler might combine the store to 'b' with other stores to 'b'.723Either can result in highly counterintuitive effects on ordering.724 725Worse yet, if the compiler is able to prove (say) that the value of726variable 'a' is always non-zero, it would be well within its rights727to optimize the original example by eliminating the "if" statement728as follows:729 730 q = a;731 b = 1; /* BUG: Compiler and CPU can both reorder!!! */732 733So don't leave out the READ_ONCE().734 735It is tempting to try to enforce ordering on identical stores on both736branches of the "if" statement as follows:737 738 q = READ_ONCE(a);739 if (q) {740 barrier();741 WRITE_ONCE(b, 1);742 do_something();743 } else {744 barrier();745 WRITE_ONCE(b, 1);746 do_something_else();747 }748 749Unfortunately, current compilers will transform this as follows at high750optimization levels:751 752 q = READ_ONCE(a);753 barrier();754 WRITE_ONCE(b, 1); /* BUG: No ordering vs. load from a!!! */755 if (q) {756 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */757 do_something();758 } else {759 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */760 do_something_else();761 }762 763Now there is no conditional between the load from 'a' and the store to764'b', which means that the CPU is within its rights to reorder them:765The conditional is absolutely required, and must be present in the766assembly code even after all compiler optimizations have been applied.767Therefore, if you need ordering in this example, you need explicit768memory barriers, for example, smp_store_release():769 770 q = READ_ONCE(a);771 if (q) {772 smp_store_release(&b, 1);773 do_something();774 } else {775 smp_store_release(&b, 1);776 do_something_else();777 }778 779In contrast, without explicit memory barriers, two-legged-if control780ordering is guaranteed only when the stores differ, for example:781 782 q = READ_ONCE(a);783 if (q) {784 WRITE_ONCE(b, 1);785 do_something();786 } else {787 WRITE_ONCE(b, 2);788 do_something_else();789 }790 791The initial READ_ONCE() is still required to prevent the compiler from792proving the value of 'a'.793 794In addition, you need to be careful what you do with the local variable 'q',795otherwise the compiler might be able to guess the value and again remove796the needed conditional. For example:797 798 q = READ_ONCE(a);799 if (q % MAX) {800 WRITE_ONCE(b, 1);801 do_something();802 } else {803 WRITE_ONCE(b, 2);804 do_something_else();805 }806 807If MAX is defined to be 1, then the compiler knows that (q % MAX) is808equal to zero, in which case the compiler is within its rights to809transform the above code into the following:810 811 q = READ_ONCE(a);812 WRITE_ONCE(b, 2);813 do_something_else();814 815Given this transformation, the CPU is not required to respect the ordering816between the load from variable 'a' and the store to variable 'b'. It is817tempting to add a barrier(), but this does not help. The conditional818is gone, and the barrier won't bring it back. Therefore, if you are819relying on this ordering, you should make sure that MAX is greater than820one, perhaps as follows:821 822 q = READ_ONCE(a);823 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */824 if (q % MAX) {825 WRITE_ONCE(b, 1);826 do_something();827 } else {828 WRITE_ONCE(b, 2);829 do_something_else();830 }831 832Please note once again that the stores to 'b' differ. If they were833identical, as noted earlier, the compiler could pull this store outside834of the 'if' statement.835 836You must also be careful not to rely too much on boolean short-circuit837evaluation. Consider this example:838 839 q = READ_ONCE(a);840 if (q || 1 > 0)841 WRITE_ONCE(b, 1);842 843Because the first condition cannot fault and the second condition is844always true, the compiler can transform this example as following,845defeating control dependency:846 847 q = READ_ONCE(a);848 WRITE_ONCE(b, 1);849 850This example underscores the need to ensure that the compiler cannot851out-guess your code. More generally, although READ_ONCE() does force852the compiler to actually emit code for a given load, it does not force853the compiler to use the results.854 855In addition, control dependencies apply only to the then-clause and856else-clause of the if-statement in question. In particular, it does857not necessarily apply to code following the if-statement:858 859 q = READ_ONCE(a);860 if (q) {861 WRITE_ONCE(b, 1);862 } else {863 WRITE_ONCE(b, 2);864 }865 WRITE_ONCE(c, 1); /* BUG: No ordering against the read from 'a'. */866 867It is tempting to argue that there in fact is ordering because the868compiler cannot reorder volatile accesses and also cannot reorder869the writes to 'b' with the condition. Unfortunately for this line870of reasoning, the compiler might compile the two writes to 'b' as871conditional-move instructions, as in this fanciful pseudo-assembly872language:873 874 ld r1,a875 cmp r1,$0876 cmov,ne r4,$1877 cmov,eq r4,$2878 st r4,b879 st $1,c880 881A weakly ordered CPU would have no dependency of any sort between the load882from 'a' and the store to 'c'. The control dependencies would extend883only to the pair of cmov instructions and the store depending on them.884In short, control dependencies apply only to the stores in the then-clause885and else-clause of the if-statement in question (including functions886invoked by those two clauses), not to code following that if-statement.887 888 889Note well that the ordering provided by a control dependency is local890to the CPU containing it. See the section on "Multicopy atomicity"891for more information.892 893 894In summary:895 896 (*) Control dependencies can order prior loads against later stores.897 However, they do -not- guarantee any other sort of ordering:898 Not prior loads against later loads, nor prior stores against899 later anything. If you need these other forms of ordering,900 use smp_rmb(), smp_wmb(), or, in the case of prior stores and901 later loads, smp_mb().902 903 (*) If both legs of the "if" statement begin with identical stores to904 the same variable, then those stores must be ordered, either by905 preceding both of them with smp_mb() or by using smp_store_release()906 to carry out the stores. Please note that it is -not- sufficient907 to use barrier() at beginning of each leg of the "if" statement908 because, as shown by the example above, optimizing compilers can909 destroy the control dependency while respecting the letter of the910 barrier() law.911 912 (*) Control dependencies require at least one run-time conditional913 between the prior load and the subsequent store, and this914 conditional must involve the prior load. If the compiler is able915 to optimize the conditional away, it will have also optimized916 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()917 can help to preserve the needed conditional.918 919 (*) Control dependencies require that the compiler avoid reordering the920 dependency into nonexistence. Careful use of READ_ONCE() or921 atomic{,64}_read() can help to preserve your control dependency.922 Please see the COMPILER BARRIER section for more information.923 924 (*) Control dependencies apply only to the then-clause and else-clause925 of the if-statement containing the control dependency, including926 any functions that these two clauses call. Control dependencies927 do -not- apply to code following the if-statement containing the928 control dependency.929 930 (*) Control dependencies pair normally with other types of barriers.931 932 (*) Control dependencies do -not- provide multicopy atomicity. If you933 need all the CPUs to see a given store at the same time, use smp_mb().934 935 (*) Compilers do not understand control dependencies. It is therefore936 your job to ensure that they do not break your code.937 938 939SMP BARRIER PAIRING940-------------------941 942When dealing with CPU-CPU interactions, certain types of memory barrier should943always be paired. A lack of appropriate pairing is almost certainly an error.944 945General barriers pair with each other, though they also pair with most946other types of barriers, albeit without multicopy atomicity. An acquire947barrier pairs with a release barrier, but both may also pair with other948barriers, including of course general barriers. A write barrier pairs949with an address-dependency barrier, a control dependency, an acquire barrier,950a release barrier, a read barrier, or a general barrier. Similarly a951read barrier, control dependency, or an address-dependency barrier pairs952with a write barrier, an acquire barrier, a release barrier, or a953general barrier:954 955 CPU 1 CPU 2956 =============== ===============957 WRITE_ONCE(a, 1);958 <write barrier>959 WRITE_ONCE(b, 2); x = READ_ONCE(b);960 <read barrier>961 y = READ_ONCE(a);962 963Or:964 965 CPU 1 CPU 2966 =============== ===============================967 a = 1;968 <write barrier>969 WRITE_ONCE(b, &a); x = READ_ONCE(b);970 <implicit address-dependency barrier>971 y = *x;972 973Or even:974 975 CPU 1 CPU 2976 =============== ===============================977 r1 = READ_ONCE(y);978 <general barrier>979 WRITE_ONCE(x, 1); if (r2 = READ_ONCE(x)) {980 <implicit control dependency>981 WRITE_ONCE(y, 1);982 }983 984 assert(r1 == 0 || r2 == 0);985 986Basically, the read barrier always has to be there, even though it can be of987the "weaker" type.988 989[!] Note that the stores before the write barrier would normally be expected to990match the loads after the read barrier or the address-dependency barrier, and991vice versa:992 993 CPU 1 CPU 2994 =================== ===================995 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);996 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);997 <write barrier> \ <read barrier>998 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);999 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);1000 1001 1002EXAMPLES OF MEMORY BARRIER SEQUENCES1003------------------------------------1004 1005Firstly, write barriers act as partial orderings on store operations.1006Consider the following sequence of events:1007 1008 CPU 11009 =======================1010 STORE A = 11011 STORE B = 21012 STORE C = 31013 <write barrier>1014 STORE D = 41015 STORE E = 51016 1017This sequence of events is committed to the memory coherence system in an order1018that the rest of the system might perceive as the unordered set of { STORE A,1019STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E1020}:1021 1022 +-------+ : :1023 | | +------+1024 | |------>| C=3 | } /\1025 | | : +------+ }----- \ -----> Events perceptible to1026 | | : | A=1 | } \/ the rest of the system1027 | | : +------+ }1028 | CPU 1 | : | B=2 | }1029 | | +------+ }1030 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier1031 | | +------+ } requires all stores prior to the1032 | | : | E=5 | } barrier to be committed before1033 | | : +------+ } further stores may take place1034 | |------>| D=4 | }1035 | | +------+1036 +-------+ : :1037 |1038 | Sequence in which stores are committed to the1039 | memory system by CPU 11040 V1041 1042 1043Secondly, address-dependency barriers act as partial orderings on address-1044dependent loads. Consider the following sequence of events:1045 1046 CPU 1 CPU 21047 ======================= =======================1048 { B = 7; X = 9; Y = 8; C = &Y }1049 STORE A = 11050 STORE B = 21051 <write barrier>1052 STORE C = &B LOAD X1053 STORE D = 4 LOAD C (gets &B)1054 LOAD *C (reads B)1055 1056Without intervention, CPU 2 may perceive the events on CPU 1 in some1057effectively random order, despite the write barrier issued by CPU 1:1058 1059 +-------+ : : : :1060 | | +------+ +-------+ | Sequence of update1061 | |------>| B=2 |----- --->| Y->8 | | of perception on1062 | | : +------+ \ +-------+ | CPU 21063 | CPU 1 | : | A=1 | \ --->| C->&Y | V1064 | | +------+ | +-------+1065 | | wwwwwwwwwwwwwwww | : :1066 | | +------+ | : :1067 | | : | C=&B |--- | : : +-------+1068 | | : +------+ \ | +-------+ | |1069 | |------>| D=4 | ----------->| C->&B |------>| |1070 | | +------+ | +-------+ | |1071 +-------+ : : | : : | |1072 | : : | |1073 | : : | CPU 2 |1074 | +-------+ | |1075 Apparently incorrect ---> | | B->7 |------>| |1076 perception of B (!) | +-------+ | |1077 | : : | |1078 | +-------+ | |1079 The load of X holds ---> \ | X->9 |------>| |1080 up the maintenance \ +-------+ | |1081 of coherence of B ----->| B->2 | +-------+1082 +-------+1083 : :1084 1085 1086In the above example, CPU 2 perceives that B is 7, despite the load of *C1087(which would be B) coming after the LOAD of C.1088 1089If, however, an address-dependency barrier were to be placed between the load1090of C and the load of *C (ie: B) on CPU 2:1091 1092 CPU 1 CPU 21093 ======================= =======================1094 { B = 7; X = 9; Y = 8; C = &Y }1095 STORE A = 11096 STORE B = 21097 <write barrier>1098 STORE C = &B LOAD X1099 STORE D = 4 LOAD C (gets &B)1100 <address-dependency barrier>1101 LOAD *C (reads B)1102 1103then the following will occur:1104 1105 +-------+ : : : :1106 | | +------+ +-------+1107 | |------>| B=2 |----- --->| Y->8 |1108 | | : +------+ \ +-------+1109 | CPU 1 | : | A=1 | \ --->| C->&Y |1110 | | +------+ | +-------+1111 | | wwwwwwwwwwwwwwww | : :1112 | | +------+ | : :1113 | | : | C=&B |--- | : : +-------+1114 | | : +------+ \ | +-------+ | |1115 | |------>| D=4 | ----------->| C->&B |------>| |1116 | | +------+ | +-------+ | |1117 +-------+ : : | : : | |1118 | : : | |1119 | : : | CPU 2 |1120 | +-------+ | |1121 | | X->9 |------>| |1122 | +-------+ | |1123 Makes sure all effects ---> \ aaaaaaaaaaaaaaaaa | |1124 prior to the store of C \ +-------+ | |1125 are perceptible to ----->| B->2 |------>| |1126 subsequent loads +-------+ | |1127 : : +-------+1128 1129 1130And thirdly, a read barrier acts as a partial order on loads. Consider the1131following sequence of events:1132 1133 CPU 1 CPU 21134 ======================= =======================1135 { A = 0, B = 9 }1136 STORE A=11137 <write barrier>1138 STORE B=21139 LOAD B1140 LOAD A1141 1142Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in1143some effectively random order, despite the write barrier issued by CPU 1:1144 1145 +-------+ : : : :1146 | | +------+ +-------+1147 | |------>| A=1 |------ --->| A->0 |1148 | | +------+ \ +-------+1149 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |1150 | | +------+ | +-------+1151 | |------>| B=2 |--- | : :1152 | | +------+ \ | : : +-------+1153 +-------+ : : \ | +-------+ | |1154 ---------->| B->2 |------>| |1155 | +-------+ | CPU 2 |1156 | | A->0 |------>| |1157 | +-------+ | |1158 | : : +-------+1159 \ : :1160 \ +-------+1161 ---->| A->1 |1162 +-------+1163 : :1164 1165 1166If, however, a read barrier were to be placed between the load of B and the1167load of A on CPU 2:1168 1169 CPU 1 CPU 21170 ======================= =======================1171 { A = 0, B = 9 }1172 STORE A=11173 <write barrier>1174 STORE B=21175 LOAD B1176 <read barrier>1177 LOAD A1178 1179then the partial ordering imposed by CPU 1 will be perceived correctly by CPU11802:1181 1182 +-------+ : : : :1183 | | +------+ +-------+1184 | |------>| A=1 |------ --->| A->0 |1185 | | +------+ \ +-------+1186 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |1187 | | +------+ | +-------+1188 | |------>| B=2 |--- | : :1189 | | +------+ \ | : : +-------+1190 +-------+ : : \ | +-------+ | |1191 ---------->| B->2 |------>| |1192 | +-------+ | CPU 2 |1193 | : : | |1194 | : : | |1195 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |1196 barrier causes all effects \ +-------+ | |1197 prior to the storage of B ---->| A->1 |------>| |1198 to be perceptible to CPU 2 +-------+ | |1199 : : +-------+1200 1201 1202To illustrate this more completely, consider what could happen if the code1203contained a load of A either side of the read barrier:1204 1205 CPU 1 CPU 21206 ======================= =======================1207 { A = 0, B = 9 }1208 STORE A=11209 <write barrier>1210 STORE B=21211 LOAD B1212 LOAD A [first load of A]1213 <read barrier>1214 LOAD A [second load of A]1215 1216Even though the two loads of A both occur after the load of B, they may both1217come up with different values:1218 1219 +-------+ : : : :1220 | | +------+ +-------+1221 | |------>| A=1 |------ --->| A->0 |1222 | | +------+ \ +-------+1223 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |1224 | | +------+ | +-------+1225 | |------>| B=2 |--- | : :1226 | | +------+ \ | : : +-------+1227 +-------+ : : \ | +-------+ | |1228 ---------->| B->2 |------>| |1229 | +-------+ | CPU 2 |1230 | : : | |1231 | : : | |1232 | +-------+ | |1233 | | A->0 |------>| 1st |1234 | +-------+ | |1235 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |1236 barrier causes all effects \ +-------+ | |1237 prior to the storage of B ---->| A->1 |------>| 2nd |1238 to be perceptible to CPU 2 +-------+ | |1239 : : +-------+1240 1241 1242But it may be that the update to A from CPU 1 becomes perceptible to CPU 21243before the read barrier completes anyway:1244 1245 +-------+ : : : :1246 | | +------+ +-------+1247 | |------>| A=1 |------ --->| A->0 |1248 | | +------+ \ +-------+1249 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |1250 | | +------+ | +-------+1251 | |------>| B=2 |--- | : :1252 | | +------+ \ | : : +-------+1253 +-------+ : : \ | +-------+ | |1254 ---------->| B->2 |------>| |1255 | +-------+ | CPU 2 |1256 | : : | |1257 \ : : | |1258 \ +-------+ | |1259 ---->| A->1 |------>| 1st |1260 +-------+ | |1261 rrrrrrrrrrrrrrrrr | |1262 +-------+ | |1263 | A->1 |------>| 2nd |1264 +-------+ | |1265 : : +-------+1266 1267 1268The guarantee is that the second load will always come up with A == 1 if the1269load of B came up with B == 2. No such guarantee exists for the first load of1270A; that may come up with either A == 0 or A == 1.1271 1272 1273READ MEMORY BARRIERS VS LOAD SPECULATION1274----------------------------------------1275 1276Many CPUs speculate with loads: that is they see that they will need to load an1277item from memory, and they find a time where they're not using the bus for any1278other loads, and so do the load in advance - even though they haven't actually1279got to that point in the instruction execution flow yet. This permits the1280actual load instruction to potentially complete immediately because the CPU1281already has the value to hand.1282 1283It may turn out that the CPU didn't actually need the value - perhaps because a1284branch circumvented the load - in which case it can discard the value or just1285cache it for later use.1286 1287Consider:1288 1289 CPU 1 CPU 21290 ======================= =======================1291 LOAD B1292 DIVIDE } Divide instructions generally1293 DIVIDE } take a long time to perform1294 LOAD A1295 1296Which might appear as this:1297 1298 : : +-------+1299 +-------+ | |1300 --->| B->2 |------>| |1301 +-------+ | CPU 2 |1302 : :DIVIDE | |1303 +-------+ | |1304 The CPU being busy doing a ---> --->| A->0 |~~~~ | |1305 division speculates on the +-------+ ~ | |1306 LOAD of A : : ~ | |1307 : :DIVIDE | |1308 : : ~ | |1309 Once the divisions are complete --> : : ~-->| |1310 the CPU can then perform the : : | |1311 LOAD with immediate effect : : +-------+1312 1313 1314Placing a read barrier or an address-dependency barrier just before the second1315load:1316 1317 CPU 1 CPU 21318 ======================= =======================1319 LOAD B1320 DIVIDE1321 DIVIDE1322 <read barrier>1323 LOAD A1324 1325will force any value speculatively obtained to be reconsidered to an extent1326dependent on the type of barrier used. If there was no change made to the1327speculated memory location, then the speculated value will just be used:1328 1329 : : +-------+1330 +-------+ | |1331 --->| B->2 |------>| |1332 +-------+ | CPU 2 |1333 : :DIVIDE | |1334 +-------+ | |1335 The CPU being busy doing a ---> --->| A->0 |~~~~ | |1336 division speculates on the +-------+ ~ | |1337 LOAD of A : : ~ | |1338 : :DIVIDE | |1339 : : ~ | |1340 : : ~ | |1341 rrrrrrrrrrrrrrrr~ | |1342 : : ~ | |1343 : : ~-->| |1344 : : | |1345 : : +-------+1346 1347 1348but if there was an update or an invalidation from another CPU pending, then1349the speculation will be cancelled and the value reloaded:1350 1351 : : +-------+1352 +-------+ | |1353 --->| B->2 |------>| |1354 +-------+ | CPU 2 |1355 : :DIVIDE | |1356 +-------+ | |1357 The CPU being busy doing a ---> --->| A->0 |~~~~ | |1358 division speculates on the +-------+ ~ | |1359 LOAD of A : : ~ | |1360 : :DIVIDE | |1361 : : ~ | |1362 : : ~ | |1363 rrrrrrrrrrrrrrrrr | |1364 +-------+ | |1365 The speculation is discarded ---> --->| A->1 |------>| |1366 and an updated value is +-------+ | |1367 retrieved : : +-------+1368 1369 1370MULTICOPY ATOMICITY1371--------------------1372 1373Multicopy atomicity is a deeply intuitive notion about ordering that is1374not always provided by real computer systems, namely that a given store1375becomes visible at the same time to all CPUs, or, alternatively, that all1376CPUs agree on the order in which all stores become visible. However,1377support of full multicopy atomicity would rule out valuable hardware1378optimizations, so a weaker form called ``other multicopy atomicity''1379instead guarantees only that a given store becomes visible at the same1380time to all -other- CPUs. The remainder of this document discusses this1381weaker form, but for brevity will call it simply ``multicopy atomicity''.1382 1383The following example demonstrates multicopy atomicity:1384 1385 CPU 1 CPU 2 CPU 31386 ======================= ======================= =======================1387 { X = 0, Y = 0 }1388 STORE X=1 r1=LOAD X (reads 1) LOAD Y (reads 1)1389 <general barrier> <read barrier>1390 STORE Y=r1 LOAD X1391 1392Suppose that CPU 2's load from X returns 1, which it then stores to Y,1393and CPU 3's load from Y returns 1. This indicates that CPU 1's store1394to X precedes CPU 2's load from X and that CPU 2's store to Y precedes1395CPU 3's load from Y. In addition, the memory barriers guarantee that1396CPU 2 executes its load before its store, and CPU 3 loads from Y before1397it loads from X. The question is then "Can CPU 3's load from X return 0?"1398 1399Because CPU 3's load from X in some sense comes after CPU 2's load, it1400is natural to expect that CPU 3's load from X must therefore return 1.1401This expectation follows from multicopy atomicity: if a load executing1402on CPU B follows a load from the same variable executing on CPU A (and1403CPU A did not originally store the value which it read), then on1404multicopy-atomic systems, CPU B's load must return either the same value1405that CPU A's load did or some later value. However, the Linux kernel1406does not require systems to be multicopy atomic.1407 1408The use of a general memory barrier in the example above compensates1409for any lack of multicopy atomicity. In the example, if CPU 2's load1410from X returns 1 and CPU 3's load from Y returns 1, then CPU 3's load1411from X must indeed also return 1.1412 1413However, dependencies, read barriers, and write barriers are not always1414able to compensate for non-multicopy atomicity. For example, suppose1415that CPU 2's general barrier is removed from the above example, leaving1416only the data dependency shown below:1417 1418 CPU 1 CPU 2 CPU 31419 ======================= ======================= =======================1420 { X = 0, Y = 0 }1421 STORE X=1 r1=LOAD X (reads 1) LOAD Y (reads 1)1422 <data dependency> <read barrier>1423 STORE Y=r1 LOAD X (reads 0)1424 1425This substitution allows non-multicopy atomicity to run rampant: in1426this example, it is perfectly legal for CPU 2's load from X to return 1,1427CPU 3's load from Y to return 1, and its load from X to return 0.1428 1429The key point is that although CPU 2's data dependency orders its load1430and store, it does not guarantee to order CPU 1's store. Thus, if this1431example runs on a non-multicopy-atomic system where CPUs 1 and 2 share a1432store buffer or a level of cache, CPU 2 might have early access to CPU 1's1433writes. General barriers are therefore required to ensure that all CPUs1434agree on the combined order of multiple accesses.1435 1436General barriers can compensate not only for non-multicopy atomicity,1437but can also generate additional ordering that can ensure that -all-1438CPUs will perceive the same order of -all- operations. In contrast, a1439chain of release-acquire pairs do not provide this additional ordering,1440which means that only those CPUs on the chain are guaranteed to agree1441on the combined order of the accesses. For example, switching to C code1442in deference to the ghost of Herman Hollerith:1443 1444 int u, v, x, y, z;1445 1446 void cpu0(void)1447 {1448 r0 = smp_load_acquire(&x);1449 WRITE_ONCE(u, 1);1450 smp_store_release(&y, 1);1451 }1452 1453 void cpu1(void)1454 {1455 r1 = smp_load_acquire(&y);1456 r4 = READ_ONCE(v);1457 r5 = READ_ONCE(u);1458 smp_store_release(&z, 1);1459 }1460 1461 void cpu2(void)1462 {1463 r2 = smp_load_acquire(&z);1464 smp_store_release(&x, 1);1465 }1466 1467 void cpu3(void)1468 {1469 WRITE_ONCE(v, 1);1470 smp_mb();1471 r3 = READ_ONCE(u);1472 }1473 1474Because cpu0(), cpu1(), and cpu2() participate in a chain of1475smp_store_release()/smp_load_acquire() pairs, the following outcome1476is prohibited:1477 1478 r0 == 1 && r1 == 1 && r2 == 11479 1480Furthermore, because of the release-acquire relationship between cpu0()1481and cpu1(), cpu1() must see cpu0()'s writes, so that the following1482outcome is prohibited:1483 1484 r1 == 1 && r5 == 01485 1486However, the ordering provided by a release-acquire chain is local1487to the CPUs participating in that chain and does not apply to cpu3(),1488at least aside from stores. Therefore, the following outcome is possible:1489 1490 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 01491 1492As an aside, the following outcome is also possible:1493 1494 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 11495 1496Although cpu0(), cpu1(), and cpu2() will see their respective reads and1497writes in order, CPUs not involved in the release-acquire chain might1498well disagree on the order. This disagreement stems from the fact that1499the weak memory-barrier instructions used to implement smp_load_acquire()1500and smp_store_release() are not required to order prior stores against1501subsequent loads in all cases. This means that cpu3() can see cpu0()'s1502store to u as happening -after- cpu1()'s load from v, even though1503both cpu0() and cpu1() agree that these two operations occurred in the1504intended order.1505 1506However, please keep in mind that smp_load_acquire() is not magic.1507In particular, it simply reads from its argument with ordering. It does1508-not- ensure that any particular value will be read. Therefore, the1509following outcome is possible:1510 1511 r0 == 0 && r1 == 0 && r2 == 0 && r5 == 01512 1513Note that this outcome can happen even on a mythical sequentially1514consistent system where nothing is ever reordered.1515 1516To reiterate, if your code requires full ordering of all operations,1517use general barriers throughout.1518 1519 1520========================1521EXPLICIT KERNEL BARRIERS1522========================1523 1524The Linux kernel has a variety of different barriers that act at different1525levels:1526 1527 (*) Compiler barrier.1528 1529 (*) CPU memory barriers.1530 1531 1532COMPILER BARRIER1533----------------1534 1535The Linux kernel has an explicit compiler barrier function that prevents the1536compiler from moving the memory accesses either side of it to the other side:1537 1538 barrier();1539 1540This is a general barrier -- there are no read-read or write-write1541variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be1542thought of as weak forms of barrier() that affect only the specific1543accesses flagged by the READ_ONCE() or WRITE_ONCE().1544 1545The barrier() function has the following effects:1546 1547 (*) Prevents the compiler from reordering accesses following the1548 barrier() to precede any accesses preceding the barrier().1549 One example use for this property is to ease communication between1550 interrupt-handler code and the code that was interrupted.1551 1552 (*) Within a loop, forces the compiler to load the variables used1553 in that loop's conditional on each pass through that loop.1554 1555The READ_ONCE() and WRITE_ONCE() functions can prevent any number of1556optimizations that, while perfectly safe in single-threaded code, can1557be fatal in concurrent code. Here are some examples of these sorts1558of optimizations:1559 1560 (*) The compiler is within its rights to reorder loads and stores1561 to the same variable, and in some cases, the CPU is within its1562 rights to reorder loads to the same variable. This means that1563 the following code:1564 1565 a[0] = x;1566 a[1] = x;1567 1568 Might result in an older value of x stored in a[1] than in a[0].1569 Prevent both the compiler and the CPU from doing this as follows:1570 1571 a[0] = READ_ONCE(x);1572 a[1] = READ_ONCE(x);1573 1574 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for1575 accesses from multiple CPUs to a single variable.1576 1577 (*) The compiler is within its rights to merge successive loads from1578 the same variable. Such merging can cause the compiler to "optimize"1579 the following code:1580 1581 while (tmp = a)1582 do_something_with(tmp);1583 1584 into the following code, which, although in some sense legitimate1585 for single-threaded code, is almost certainly not what the developer1586 intended:1587 1588 if (tmp = a)1589 for (;;)1590 do_something_with(tmp);1591 1592 Use READ_ONCE() to prevent the compiler from doing this to you:1593 1594 while (tmp = READ_ONCE(a))1595 do_something_with(tmp);1596 1597 (*) The compiler is within its rights to reload a variable, for example,1598 in cases where high register pressure prevents the compiler from1599 keeping all data of interest in registers. The compiler might1600 therefore optimize the variable 'tmp' out of our previous example:1601 1602 while (tmp = a)1603 do_something_with(tmp);1604 1605 This could result in the following code, which is perfectly safe in1606 single-threaded code, but can be fatal in concurrent code:1607 1608 while (a)1609 do_something_with(a);1610 1611 For example, the optimized version of this code could result in1612 passing a zero to do_something_with() in the case where the variable1613 a was modified by some other CPU between the "while" statement and1614 the call to do_something_with().1615 1616 Again, use READ_ONCE() to prevent the compiler from doing this:1617 1618 while (tmp = READ_ONCE(a))1619 do_something_with(tmp);1620 1621 Note that if the compiler runs short of registers, it might save1622 tmp onto the stack. The overhead of this saving and later restoring1623 is why compilers reload variables. Doing so is perfectly safe for1624 single-threaded code, so you need to tell the compiler about cases1625 where it is not safe.1626 1627 (*) The compiler is within its rights to omit a load entirely if it knows1628 what the value will be. For example, if the compiler can prove that1629 the value of variable 'a' is always zero, it can optimize this code:1630 1631 while (tmp = a)1632 do_something_with(tmp);1633 1634 Into this:1635 1636 do { } while (0);1637 1638 This transformation is a win for single-threaded code because it1639 gets rid of a load and a branch. The problem is that the compiler1640 will carry out its proof assuming that the current CPU is the only1641 one updating variable 'a'. If variable 'a' is shared, then the1642 compiler's proof will be erroneous. Use READ_ONCE() to tell the1643 compiler that it doesn't know as much as it thinks it does:1644 1645 while (tmp = READ_ONCE(a))1646 do_something_with(tmp);1647 1648 But please note that the compiler is also closely watching what you1649 do with the value after the READ_ONCE(). For example, suppose you1650 do the following and MAX is a preprocessor macro with the value 1:1651 1652 while ((tmp = READ_ONCE(a)) % MAX)1653 do_something_with(tmp);1654 1655 Then the compiler knows that the result of the "%" operator applied1656 to MAX will always be zero, again allowing the compiler to optimize1657 the code into near-nonexistence. (It will still load from the1658 variable 'a'.)1659 1660 (*) Similarly, the compiler is within its rights to omit a store entirely1661 if it knows that the variable already has the value being stored.1662 Again, the compiler assumes that the current CPU is the only one1663 storing into the variable, which can cause the compiler to do the1664 wrong thing for shared variables. For example, suppose you have1665 the following:1666 1667 a = 0;1668 ... Code that does not store to variable a ...1669 a = 0;1670 1671 The compiler sees that the value of variable 'a' is already zero, so1672 it might well omit the second store. This would come as a fatal1673 surprise if some other CPU might have stored to variable 'a' in the1674 meantime.1675 1676 Use WRITE_ONCE() to prevent the compiler from making this sort of1677 wrong guess:1678 1679 WRITE_ONCE(a, 0);1680 ... Code that does not store to variable a ...1681 WRITE_ONCE(a, 0);1682 1683 (*) The compiler is within its rights to reorder memory accesses unless1684 you tell it not to. For example, consider the following interaction1685 between process-level code and an interrupt handler:1686 1687 void process_level(void)1688 {1689 msg = get_message();1690 flag = true;1691 }1692 1693 void interrupt_handler(void)1694 {1695 if (flag)1696 process_message(msg);1697 }1698 1699 There is nothing to prevent the compiler from transforming1700 process_level() to the following, in fact, this might well be a1701 win for single-threaded code:1702 1703 void process_level(void)1704 {1705 flag = true;1706 msg = get_message();1707 }1708 1709 If the interrupt occurs between these two statement, then1710 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()1711 to prevent this as follows:1712 1713 void process_level(void)1714 {1715 WRITE_ONCE(msg, get_message());1716 WRITE_ONCE(flag, true);1717 }1718 1719 void interrupt_handler(void)1720 {1721 if (READ_ONCE(flag))1722 process_message(READ_ONCE(msg));1723 }1724 1725 Note that the READ_ONCE() and WRITE_ONCE() wrappers in1726 interrupt_handler() are needed if this interrupt handler can itself1727 be interrupted by something that also accesses 'flag' and 'msg',1728 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()1729 and WRITE_ONCE() are not needed in interrupt_handler() other than1730 for documentation purposes. (Note also that nested interrupts1731 do not typically occur in modern Linux kernels, in fact, if an1732 interrupt handler returns with interrupts enabled, you will get a1733 WARN_ONCE() splat.)1734 1735 You should assume that the compiler can move READ_ONCE() and1736 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),1737 barrier(), or similar primitives.1738 1739 This effect could also be achieved using barrier(), but READ_ONCE()1740 and WRITE_ONCE() are more selective: With READ_ONCE() and1741 WRITE_ONCE(), the compiler need only forget the contents of the1742 indicated memory locations, while with barrier() the compiler must1743 discard the value of all memory locations that it has currently1744 cached in any machine registers. Of course, the compiler must also1745 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,1746 though the CPU of course need not do so.1747 1748 (*) The compiler is within its rights to invent stores to a variable,1749 as in the following example:1750 1751 if (a)1752 b = a;1753 else1754 b = 42;1755 1756 The compiler might save a branch by optimizing this as follows:1757 1758 b = 42;1759 if (a)1760 b = a;1761 1762 In single-threaded code, this is not only safe, but also saves1763 a branch. Unfortunately, in concurrent code, this optimization1764 could cause some other CPU to see a spurious value of 42 -- even1765 if variable 'a' was never zero -- when loading variable 'b'.1766 Use WRITE_ONCE() to prevent this as follows:1767 1768 if (a)1769 WRITE_ONCE(b, a);1770 else1771 WRITE_ONCE(b, 42);1772 1773 The compiler can also invent loads. These are usually less1774 damaging, but they can result in cache-line bouncing and thus in1775 poor performance and scalability. Use READ_ONCE() to prevent1776 invented loads.1777 1778 (*) For aligned memory locations whose size allows them to be accessed1779 with a single memory-reference instruction, prevents "load tearing"1780 and "store tearing," in which a single large access is replaced by1781 multiple smaller accesses. For example, given an architecture having1782 16-bit store instructions with 7-bit immediate fields, the compiler1783 might be tempted to use two 16-bit store-immediate instructions to1784 implement the following 32-bit store:1785 1786 p = 0x00010002;1787 1788 Please note that GCC really does use this sort of optimization,1789 which is not surprising given that it would likely take more1790 than two instructions to build the constant and then store it.1791 This optimization can therefore be a win in single-threaded code.1792 In fact, a recent bug (since fixed) caused GCC to incorrectly use1793 this optimization in a volatile store. In the absence of such bugs,1794 use of WRITE_ONCE() prevents store tearing in the following example:1795 1796 WRITE_ONCE(p, 0x00010002);1797 1798 Use of packed structures can also result in load and store tearing,1799 as in this example:1800 1801 struct __attribute__((__packed__)) foo {1802 short a;1803 int b;1804 short c;1805 };1806 struct foo foo1, foo2;1807 ...1808 1809 foo2.a = foo1.a;1810 foo2.b = foo1.b;1811 foo2.c = foo1.c;1812 1813 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no1814 volatile markings, the compiler would be well within its rights to1815 implement these three assignment statements as a pair of 32-bit1816 loads followed by a pair of 32-bit stores. This would result in1817 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()1818 and WRITE_ONCE() again prevent tearing in this example:1819 1820 foo2.a = foo1.a;1821 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));1822 foo2.c = foo1.c;1823 1824All that aside, it is never necessary to use READ_ONCE() and1825WRITE_ONCE() on a variable that has been marked volatile. For example,1826because 'jiffies' is marked volatile, it is never necessary to1827say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and1828WRITE_ONCE() are implemented as volatile casts, which has no effect when1829its argument is already marked volatile.1830 1831Please note that these compiler barriers have no direct effect on the CPU,1832which may then reorder things however it wishes.1833 1834 1835CPU MEMORY BARRIERS1836-------------------1837 1838The Linux kernel has seven basic CPU memory barriers:1839 1840 TYPE MANDATORY SMP CONDITIONAL1841 ======================= =============== ===============1842 GENERAL mb() smp_mb()1843 WRITE wmb() smp_wmb()1844 READ rmb() smp_rmb()1845 ADDRESS DEPENDENCY READ_ONCE()1846 1847 1848All memory barriers except the address-dependency barriers imply a compiler1849barrier. Address dependencies do not impose any additional compiler ordering.1850 1851Aside: In the case of address dependencies, the compiler would be expected1852to issue the loads in the correct order (eg. `a[b]` would have to load1853the value of b before loading a[b]), however there is no guarantee in1854the C specification that the compiler may not speculate the value of b1855(eg. is equal to 1) and load a[b] before b (eg. tmp = a[1]; if (b != 1)1856tmp = a[b]; ). There is also the problem of a compiler reloading b after1857having loaded a[b], thus having a newer copy of b than a[b]. A consensus1858has not yet been reached about these problems, however the READ_ONCE()1859macro is a good place to start looking.1860 1861SMP memory barriers are reduced to compiler barriers on uniprocessor compiled1862systems because it is assumed that a CPU will appear to be self-consistent,1863and will order overlapping accesses correctly with respect to itself.1864However, see the subsection on "Virtual Machine Guests" below.1865 1866[!] Note that SMP memory barriers _must_ be used to control the ordering of1867references to shared memory on SMP systems, though the use of locking instead1868is sufficient.1869 1870Mandatory barriers should not be used to control SMP effects, since mandatory1871barriers impose unnecessary overhead on both SMP and UP systems. They may,1872however, be used to control MMIO effects on accesses through relaxed memory I/O1873windows. These barriers are required even on non-SMP systems as they affect1874the order in which memory operations appear to a device by prohibiting both the1875compiler and the CPU from reordering them.1876 1877 1878There are some more advanced barrier functions:1879 1880 (*) smp_store_mb(var, value)1881 1882 This assigns the value to the variable and then inserts a full memory1883 barrier after it. It isn't guaranteed to insert anything more than a1884 compiler barrier in a UP compilation.1885 1886 1887 (*) smp_mb__before_atomic();1888 (*) smp_mb__after_atomic();1889 1890 These are for use with atomic RMW functions that do not imply memory1891 barriers, but where the code needs a memory barrier. Examples for atomic1892 RMW functions that do not imply a memory barrier are e.g. add,1893 subtract, (failed) conditional operations, _relaxed functions,1894 but not atomic_read or atomic_set. A common example where a memory1895 barrier may be required is when atomic ops are used for reference1896 counting.1897 1898 These are also used for atomic RMW bitop functions that do not imply a1899 memory barrier (such as set_bit and clear_bit).1900 1901 As an example, consider a piece of code that marks an object as being dead1902 and then decrements the object's reference count:1903 1904 obj->dead = 1;1905 smp_mb__before_atomic();1906 atomic_dec(&obj->ref_count);1907 1908 This makes sure that the death mark on the object is perceived to be set1909 *before* the reference counter is decremented.1910 1911 See Documentation/atomic_{t,bitops}.txt for more information.1912 1913 1914 (*) dma_wmb();1915 (*) dma_rmb();1916 (*) dma_mb();1917 1918 These are for use with consistent memory to guarantee the ordering1919 of writes or reads of shared memory accessible to both the CPU and a1920 DMA capable device. See Documentation/core-api/dma-api.rst file for more1921 information about consistent memory.1922 1923 For example, consider a device driver that shares memory with a device1924 and uses a descriptor status value to indicate if the descriptor belongs1925 to the device or the CPU, and a doorbell to notify it when new1926 descriptors are available:1927 1928 if (desc->status != DEVICE_OWN) {1929 /* do not read data until we own descriptor */1930 dma_rmb();1931 1932 /* read/modify data */1933 read_data = desc->data;1934 desc->data = write_data;1935 1936 /* flush modifications before status update */1937 dma_wmb();1938 1939 /* assign ownership */1940 desc->status = DEVICE_OWN;1941 1942 /* Make descriptor status visible to the device followed by1943 * notify device of new descriptor1944 */1945 writel(DESC_NOTIFY, doorbell);1946 }1947 1948 The dma_rmb() allows us to guarantee that the device has released ownership1949 before we read the data from the descriptor, and the dma_wmb() allows1950 us to guarantee the data is written to the descriptor before the device1951 can see it now has ownership. The dma_mb() implies both a dma_rmb() and1952 a dma_wmb().1953 1954 Note that the dma_*() barriers do not provide any ordering guarantees for1955 accesses to MMIO regions. See the later "KERNEL I/O BARRIER EFFECTS"1956 subsection for more information about I/O accessors and MMIO ordering.1957 1958 (*) pmem_wmb();1959 1960 This is for use with persistent memory to ensure that stores for which1961 modifications are written to persistent storage reached a platform1962 durability domain.1963 1964 For example, after a non-temporal write to pmem region, we use pmem_wmb()1965 to ensure that stores have reached a platform durability domain. This ensures1966 that stores have updated persistent storage before any data access or1967 data transfer caused by subsequent instructions is initiated. This is1968 in addition to the ordering done by wmb().1969 1970 For load from persistent memory, existing read memory barriers are sufficient1971 to ensure read ordering.1972 1973 (*) io_stop_wc();1974 1975 For memory accesses with write-combining attributes (e.g. those returned1976 by ioremap_wc()), the CPU may wait for prior accesses to be merged with1977 subsequent ones. io_stop_wc() can be used to prevent the merging of1978 write-combining memory accesses before this macro with those after it when1979 such wait has performance implications.1980 1981===============================1982IMPLICIT KERNEL MEMORY BARRIERS1983===============================1984 1985Some of the other functions in the linux kernel imply memory barriers, amongst1986which are locking and scheduling functions.1987 1988This specification is a _minimum_ guarantee; any particular architecture may1989provide more substantial guarantees, but these may not be relied upon outside1990of arch specific code.1991 1992 1993LOCK ACQUISITION FUNCTIONS1994--------------------------1995 1996The Linux kernel has a number of locking constructs:1997 1998 (*) spin locks1999 (*) R/W spin locks2000 (*) mutexes2001 (*) semaphores2002 (*) R/W semaphores2003 2004In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations2005for each construct. These operations all imply certain barriers:2006 2007 (1) ACQUIRE operation implication:2008 2009 Memory operations issued after the ACQUIRE will be completed after the2010 ACQUIRE operation has completed.2011 2012 Memory operations issued before the ACQUIRE may be completed after2013 the ACQUIRE operation has completed.2014 2015 (2) RELEASE operation implication:2016 2017 Memory operations issued before the RELEASE will be completed before the2018 RELEASE operation has completed.2019 2020 Memory operations issued after the RELEASE may be completed before the2021 RELEASE operation has completed.2022 2023 (3) ACQUIRE vs ACQUIRE implication:2024 2025 All ACQUIRE operations issued before another ACQUIRE operation will be2026 completed before that ACQUIRE operation.2027 2028 (4) ACQUIRE vs RELEASE implication:2029 2030 All ACQUIRE operations issued before a RELEASE operation will be2031 completed before the RELEASE operation.2032 2033 (5) Failed conditional ACQUIRE implication:2034 2035 Certain locking variants of the ACQUIRE operation may fail, either due to2036 being unable to get the lock immediately, or due to receiving an unblocked2037 signal while asleep waiting for the lock to become available. Failed2038 locks do not imply any sort of barrier.2039 2040[!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only2041one-way barriers is that the effects of instructions outside of a critical2042section may seep into the inside of the critical section.2043 2044An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier2045because it is possible for an access preceding the ACQUIRE to happen after the2046ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and2047the two accesses can themselves then cross:2048 2049 *A = a;2050 ACQUIRE M2051 RELEASE M2052 *B = b;2053 2054may occur as:2055 2056 ACQUIRE M, STORE *B, STORE *A, RELEASE M2057 2058When the ACQUIRE and RELEASE are a lock acquisition and release,2059respectively, this same reordering can occur if the lock's ACQUIRE and2060RELEASE are to the same lock variable, but only from the perspective of2061another CPU not holding that lock. In short, a ACQUIRE followed by an2062RELEASE may -not- be assumed to be a full memory barrier.2063 2064Similarly, the reverse case of a RELEASE followed by an ACQUIRE does2065not imply a full memory barrier. Therefore, the CPU's execution of the2066critical sections corresponding to the RELEASE and the ACQUIRE can cross,2067so that:2068 2069 *A = a;2070 RELEASE M2071 ACQUIRE N2072 *B = b;2073 2074could occur as:2075 2076 ACQUIRE N, STORE *B, STORE *A, RELEASE M2077 2078It might appear that this reordering could introduce a deadlock.2079However, this cannot happen because if such a deadlock threatened,2080the RELEASE would simply complete, thereby avoiding the deadlock.2081 2082 Why does this work?2083 2084 One key point is that we are only talking about the CPU doing2085 the reordering, not the compiler. If the compiler (or, for2086 that matter, the developer) switched the operations, deadlock2087 -could- occur.2088 2089 But suppose the CPU reordered the operations. In this case,2090 the unlock precedes the lock in the assembly code. The CPU2091 simply elected to try executing the later lock operation first.2092 If there is a deadlock, this lock operation will simply spin (or2093 try to sleep, but more on that later). The CPU will eventually2094 execute the unlock operation (which preceded the lock operation2095 in the assembly code), which will unravel the potential deadlock,2096 allowing the lock operation to succeed.2097 2098 But what if the lock is a sleeplock? In that case, the code will2099 try to enter the scheduler, where it will eventually encounter2100 a memory barrier, which will force the earlier unlock operation2101 to complete, again unraveling the deadlock. There might be2102 a sleep-unlock race, but the locking primitive needs to resolve2103 such races properly in any case.2104 2105Locks and semaphores may not provide any guarantee of ordering on UP compiled2106systems, and so cannot be counted on in such a situation to actually achieve2107anything at all - especially with respect to I/O accesses - unless combined2108with interrupt disabling operations.2109 2110See also the section on "Inter-CPU acquiring barrier effects".2111 2112 2113As an example, consider the following:2114 2115 *A = a;2116 *B = b;2117 ACQUIRE2118 *C = c;2119 *D = d;2120 RELEASE2121 *E = e;2122 *F = f;2123 2124The following sequence of events is acceptable:2125 2126 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE2127 2128 [+] Note that {*F,*A} indicates a combined access.2129 2130But none of the following are:2131 2132 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E2133 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F2134 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F2135 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E2136 2137 2138 2139INTERRUPT DISABLING FUNCTIONS2140-----------------------------2141 2142Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts2143(RELEASE equivalent) will act as compiler barriers only. So if memory or I/O2144barriers are required in such a situation, they must be provided from some2145other means.2146 2147 2148SLEEP AND WAKE-UP FUNCTIONS2149---------------------------2150 2151Sleeping and waking on an event flagged in global data can be viewed as an2152interaction between two pieces of data: the task state of the task waiting for2153the event and the global data used to indicate the event. To make sure that2154these appear to happen in the right order, the primitives to begin the process2155of going to sleep, and the primitives to initiate a wake up imply certain2156barriers.2157 2158Firstly, the sleeper normally follows something like this sequence of events:2159 2160 for (;;) {2161 set_current_state(TASK_UNINTERRUPTIBLE);2162 if (event_indicated)2163 break;2164 schedule();2165 }2166 2167A general memory barrier is interpolated automatically by set_current_state()2168after it has altered the task state:2169 2170 CPU 12171 ===============================2172 set_current_state();2173 smp_store_mb();2174 STORE current->state2175 <general barrier>2176 LOAD event_indicated2177 2178set_current_state() may be wrapped by:2179 2180 prepare_to_wait();2181 prepare_to_wait_exclusive();2182 2183which therefore also imply a general memory barrier after setting the state.2184The whole sequence above is available in various canned forms, all of which2185interpolate the memory barrier in the right place:2186 2187 wait_event();2188 wait_event_interruptible();2189 wait_event_interruptible_exclusive();2190 wait_event_interruptible_timeout();2191 wait_event_killable();2192 wait_event_timeout();2193 wait_on_bit();2194 wait_on_bit_lock();2195 2196 2197Secondly, code that performs a wake up normally follows something like this:2198 2199 event_indicated = 1;2200 wake_up(&event_wait_queue);2201 2202or:2203 2204 event_indicated = 1;2205 wake_up_process(event_daemon);2206 2207A general memory barrier is executed by wake_up() if it wakes something up.2208If it doesn't wake anything up then a memory barrier may or may not be2209executed; you must not rely on it. The barrier occurs before the task state2210is accessed, in particular, it sits between the STORE to indicate the event2211and the STORE to set TASK_RUNNING:2212 2213 CPU 1 (Sleeper) CPU 2 (Waker)2214 =============================== ===============================2215 set_current_state(); STORE event_indicated2216 smp_store_mb(); wake_up();2217 STORE current->state ...2218 <general barrier> <general barrier>2219 LOAD event_indicated if ((LOAD task->state) & TASK_NORMAL)2220 STORE task->state2221 2222where "task" is the thread being woken up and it equals CPU 1's "current".2223 2224To repeat, a general memory barrier is guaranteed to be executed by wake_up()2225if something is actually awakened, but otherwise there is no such guarantee.2226To see this, consider the following sequence of events, where X and Y are both2227initially zero:2228 2229 CPU 1 CPU 22230 =============================== ===============================2231 X = 1; Y = 1;2232 smp_mb(); wake_up();2233 LOAD Y LOAD X2234 2235If a wakeup does occur, one (at least) of the two loads must see 1. If, on2236the other hand, a wakeup does not occur, both loads might see 0.2237 2238wake_up_process() always executes a general memory barrier. The barrier again2239occurs before the task state is accessed. In particular, if the wake_up() in2240the previous snippet were replaced by a call to wake_up_process() then one of2241the two loads would be guaranteed to see 1.2242 2243The available waker functions include:2244 2245 complete();2246 wake_up();2247 wake_up_all();2248 wake_up_bit();2249 wake_up_interruptible();2250 wake_up_interruptible_all();2251 wake_up_interruptible_nr();2252 wake_up_interruptible_poll();2253 wake_up_interruptible_sync();2254 wake_up_interruptible_sync_poll();2255 wake_up_locked();2256 wake_up_locked_poll();2257 wake_up_nr();2258 wake_up_poll();2259 wake_up_process();2260 2261In terms of memory ordering, these functions all provide the same guarantees of2262a wake_up() (or stronger).2263 2264[!] Note that the memory barriers implied by the sleeper and the waker do _not_2265order multiple stores before the wake-up with respect to loads of those stored2266values after the sleeper has called set_current_state(). For instance, if the2267sleeper does:2268 2269 set_current_state(TASK_INTERRUPTIBLE);2270 if (event_indicated)2271 break;2272 __set_current_state(TASK_RUNNING);2273 do_something(my_data);2274 2275and the waker does:2276 2277 my_data = value;2278 event_indicated = 1;2279 wake_up(&event_wait_queue);2280 2281there's no guarantee that the change to event_indicated will be perceived by2282the sleeper as coming after the change to my_data. In such a circumstance, the2283code on both sides must interpolate its own memory barriers between the2284separate data accesses. Thus the above sleeper ought to do:2285 2286 set_current_state(TASK_INTERRUPTIBLE);2287 if (event_indicated) {2288 smp_rmb();2289 do_something(my_data);2290 }2291 2292and the waker should do:2293 2294 my_data = value;2295 smp_wmb();2296 event_indicated = 1;2297 wake_up(&event_wait_queue);2298 2299 2300MISCELLANEOUS FUNCTIONS2301-----------------------2302 2303Other functions that imply barriers:2304 2305 (*) schedule() and similar imply full memory barriers.2306 2307 2308===================================2309INTER-CPU ACQUIRING BARRIER EFFECTS2310===================================2311 2312On SMP systems locking primitives give a more substantial form of barrier: one2313that does affect memory access ordering on other CPUs, within the context of2314conflict on any particular lock.2315 2316 2317ACQUIRES VS MEMORY ACCESSES2318---------------------------2319 2320Consider the following: the system has a pair of spinlocks (M) and (Q), and2321three CPUs; then should the following sequence of events occur:2322 2323 CPU 1 CPU 22324 =============================== ===============================2325 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);2326 ACQUIRE M ACQUIRE Q2327 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);2328 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);2329 RELEASE M RELEASE Q2330 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);2331 2332Then there is no guarantee as to what order CPU 3 will see the accesses to *A2333through *H occur in, other than the constraints imposed by the separate locks2334on the separate CPUs. It might, for example, see:2335 2336 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M2337 2338But it won't see any of:2339 2340 *B, *C or *D preceding ACQUIRE M2341 *A, *B or *C following RELEASE M2342 *F, *G or *H preceding ACQUIRE Q2343 *E, *F or *G following RELEASE Q2344 2345 2346=================================2347WHERE ARE MEMORY BARRIERS NEEDED?2348=================================2349 2350Under normal operation, memory operation reordering is generally not going to2351be a problem as a single-threaded linear piece of code will still appear to2352work correctly, even if it's in an SMP kernel. There are, however, four2353circumstances in which reordering definitely _could_ be a problem:2354 2355 (*) Interprocessor interaction.2356 2357 (*) Atomic operations.2358 2359 (*) Accessing devices.2360 2361 (*) Interrupts.2362 2363 2364INTERPROCESSOR INTERACTION2365--------------------------2366 2367When there's a system with more than one processor, more than one CPU in the2368system may be working on the same data set at the same time. This can cause2369synchronisation problems, and the usual way of dealing with them is to use2370locks. Locks, however, are quite expensive, and so it may be preferable to2371operate without the use of a lock if at all possible. In such a case2372operations that affect both CPUs may have to be carefully ordered to prevent2373a malfunction.2374 2375Consider, for example, the R/W semaphore slow path. Here a waiting process is2376queued on the semaphore, by virtue of it having a piece of its stack linked to2377the semaphore's list of waiting processes:2378 2379 struct rw_semaphore {2380 ...2381 spinlock_t lock;2382 struct list_head waiters;2383 };2384 2385 struct rwsem_waiter {2386 struct list_head list;2387 struct task_struct *task;2388 };2389 2390To wake up a particular waiter, the up_read() or up_write() functions have to:2391 2392 (1) read the next pointer from this waiter's record to know as to where the2393 next waiter record is;2394 2395 (2) read the pointer to the waiter's task structure;2396 2397 (3) clear the task pointer to tell the waiter it has been given the semaphore;2398 2399 (4) call wake_up_process() on the task; and2400 2401 (5) release the reference held on the waiter's task struct.2402 2403In other words, it has to perform this sequence of events:2404 2405 LOAD waiter->list.next;2406 LOAD waiter->task;2407 STORE waiter->task;2408 CALL wakeup2409 RELEASE task2410 2411and if any of these steps occur out of order, then the whole thing may2412malfunction.2413 2414Once it has queued itself and dropped the semaphore lock, the waiter does not2415get the lock again; it instead just waits for its task pointer to be cleared2416before proceeding. Since the record is on the waiter's stack, this means that2417if the task pointer is cleared _before_ the next pointer in the list is read,2418another CPU might start processing the waiter and might clobber the waiter's2419stack before the up*() function has a chance to read the next pointer.2420 2421Consider then what might happen to the above sequence of events:2422 2423 CPU 1 CPU 22424 =============================== ===============================2425 down_xxx()2426 Queue waiter2427 Sleep2428 up_yyy()2429 LOAD waiter->task;2430 STORE waiter->task;2431 Woken up by other event2432 <preempt>2433 Resume processing2434 down_xxx() returns2435 call foo()2436 foo() clobbers *waiter2437 </preempt>2438 LOAD waiter->list.next;2439 --- OOPS ---2440 2441This could be dealt with using the semaphore lock, but then the down_xxx()2442function has to needlessly get the spinlock again after being woken up.2443 2444The way to deal with this is to insert a general SMP memory barrier:2445 2446 LOAD waiter->list.next;2447 LOAD waiter->task;2448 smp_mb();2449 STORE waiter->task;2450 CALL wakeup2451 RELEASE task2452 2453In this case, the barrier makes a guarantee that all memory accesses before the2454barrier will appear to happen before all the memory accesses after the barrier2455with respect to the other CPUs on the system. It does _not_ guarantee that all2456the memory accesses before the barrier will be complete by the time the barrier2457instruction itself is complete.2458 2459On a UP system - where this wouldn't be a problem - the smp_mb() is just a2460compiler barrier, thus making sure the compiler emits the instructions in the2461right order without actually intervening in the CPU. Since there's only one2462CPU, that CPU's dependency ordering logic will take care of everything else.2463 2464 2465ATOMIC OPERATIONS2466-----------------2467 2468While they are technically interprocessor interaction considerations, atomic2469operations are noted specially as some of them imply full memory barriers and2470some don't, but they're very heavily relied on as a group throughout the2471kernel.2472 2473See Documentation/atomic_t.txt for more information.2474 2475 2476ACCESSING DEVICES2477-----------------2478 2479Many devices can be memory mapped, and so appear to the CPU as if they're just2480a set of memory locations. To control such a device, the driver usually has to2481make the right memory accesses in exactly the right order.2482 2483However, having a clever CPU or a clever compiler creates a potential problem2484in that the carefully sequenced accesses in the driver code won't reach the2485device in the requisite order if the CPU or the compiler thinks it is more2486efficient to reorder, combine or merge accesses - something that would cause2487the device to malfunction.2488 2489Inside of the Linux kernel, I/O should be done through the appropriate accessor2490routines - such as inb() or writel() - which know how to make such accesses2491appropriately sequential. While this, for the most part, renders the explicit2492use of memory barriers unnecessary, if the accessor functions are used to refer2493to an I/O memory window with relaxed memory access properties, then _mandatory_2494memory barriers are required to enforce ordering.2495 2496See Documentation/driver-api/device-io.rst for more information.2497 2498 2499INTERRUPTS2500----------2501 2502A driver may be interrupted by its own interrupt service routine, and thus the2503two parts of the driver may interfere with each other's attempts to control or2504access the device.2505 2506This may be alleviated - at least in part - by disabling local interrupts (a2507form of locking), such that the critical operations are all contained within2508the interrupt-disabled section in the driver. While the driver's interrupt2509routine is executing, the driver's core may not run on the same CPU, and its2510interrupt is not permitted to happen again until the current interrupt has been2511handled, thus the interrupt handler does not need to lock against that.2512 2513However, consider a driver that was talking to an ethernet card that sports an2514address register and a data register. If that driver's core talks to the card2515under interrupt-disablement and then the driver's interrupt handler is invoked:2516 2517 LOCAL IRQ DISABLE2518 writew(ADDR, 3);2519 writew(DATA, y);2520 LOCAL IRQ ENABLE2521 <interrupt>2522 writew(ADDR, 4);2523 q = readw(DATA);2524 </interrupt>2525 2526The store to the data register might happen after the second store to the2527address register if ordering rules are sufficiently relaxed:2528 2529 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA2530 2531 2532If ordering rules are relaxed, it must be assumed that accesses done inside an2533interrupt disabled section may leak outside of it and may interleave with2534accesses performed in an interrupt - and vice versa - unless implicit or2535explicit barriers are used.2536 2537Normally this won't be a problem because the I/O accesses done inside such2538sections will include synchronous load operations on strictly ordered I/O2539registers that form implicit I/O barriers.2540 2541 2542A similar situation may occur between an interrupt routine and two routines2543running on separate CPUs that communicate with each other. If such a case is2544likely, then interrupt-disabling locks should be used to guarantee ordering.2545 2546 2547==========================2548KERNEL I/O BARRIER EFFECTS2549==========================2550 2551Interfacing with peripherals via I/O accesses is deeply architecture and device2552specific. Therefore, drivers which are inherently non-portable may rely on2553specific behaviours of their target systems in order to achieve synchronization2554in the most lightweight manner possible. For drivers intending to be portable2555between multiple architectures and bus implementations, the kernel offers a2556series of accessor functions that provide various degrees of ordering2557guarantees:2558 2559 (*) readX(), writeX():2560 2561 The readX() and writeX() MMIO accessors take a pointer to the2562 peripheral being accessed as an __iomem * parameter. For pointers2563 mapped with the default I/O attributes (e.g. those returned by2564 ioremap()), the ordering guarantees are as follows:2565 2566 1. All readX() and writeX() accesses to the same peripheral are ordered2567 with respect to each other. This ensures that MMIO register accesses2568 by the same CPU thread to a particular device will arrive in program2569 order.2570 2571 2. A writeX() issued by a CPU thread holding a spinlock is ordered2572 before a writeX() to the same peripheral from another CPU thread2573 issued after a later acquisition of the same spinlock. This ensures2574 that MMIO register writes to a particular device issued while holding2575 a spinlock will arrive in an order consistent with acquisitions of2576 the lock.2577 2578 3. A writeX() by a CPU thread to the peripheral will first wait for the2579 completion of all prior writes to memory either issued by, or2580 propagated to, the same thread. This ensures that writes by the CPU2581 to an outbound DMA buffer allocated by dma_alloc_coherent() will be2582 visible to a DMA engine when the CPU writes to its MMIO control2583 register to trigger the transfer.2584 2585 4. A readX() by a CPU thread from the peripheral will complete before2586 any subsequent reads from memory by the same thread can begin. This2587 ensures that reads by the CPU from an incoming DMA buffer allocated2588 by dma_alloc_coherent() will not see stale data after reading from2589 the DMA engine's MMIO status register to establish that the DMA2590 transfer has completed.2591 2592 5. A readX() by a CPU thread from the peripheral will complete before2593 any subsequent delay() loop can begin execution on the same thread.2594 This ensures that two MMIO register writes by the CPU to a peripheral2595 will arrive at least 1us apart if the first write is immediately read2596 back with readX() and udelay(1) is called prior to the second2597 writeX():2598 2599 writel(42, DEVICE_REGISTER_0); // Arrives at the device...2600 readl(DEVICE_REGISTER_0);2601 udelay(1);2602 writel(42, DEVICE_REGISTER_1); // ...at least 1us before this.2603 2604 The ordering properties of __iomem pointers obtained with non-default2605 attributes (e.g. those returned by ioremap_wc()) are specific to the2606 underlying architecture and therefore the guarantees listed above cannot2607 generally be relied upon for accesses to these types of mappings.2608 2609 (*) readX_relaxed(), writeX_relaxed():2610 2611 These are similar to readX() and writeX(), but provide weaker memory2612 ordering guarantees. Specifically, they do not guarantee ordering with2613 respect to locking, normal memory accesses or delay() loops (i.e.2614 bullets 2-5 above) but they are still guaranteed to be ordered with2615 respect to other accesses from the same CPU thread to the same2616 peripheral when operating on __iomem pointers mapped with the default2617 I/O attributes.2618 2619 (*) readsX(), writesX():2620 2621 The readsX() and writesX() MMIO accessors are designed for accessing2622 register-based, memory-mapped FIFOs residing on peripherals that are not2623 capable of performing DMA. Consequently, they provide only the ordering2624 guarantees of readX_relaxed() and writeX_relaxed(), as documented above.2625 2626 (*) inX(), outX():2627 2628 The inX() and outX() accessors are intended to access legacy port-mapped2629 I/O peripherals, which may require special instructions on some2630 architectures (notably x86). The port number of the peripheral being2631 accessed is passed as an argument.2632 2633 Since many CPU architectures ultimately access these peripherals via an2634 internal virtual memory mapping, the portable ordering guarantees2635 provided by inX() and outX() are the same as those provided by readX()2636 and writeX() respectively when accessing a mapping with the default I/O2637 attributes.2638 2639 Device drivers may expect outX() to emit a non-posted write transaction2640 that waits for a completion response from the I/O peripheral before2641 returning. This is not guaranteed by all architectures and is therefore2642 not part of the portable ordering semantics.2643 2644 (*) insX(), outsX():2645 2646 As above, the insX() and outsX() accessors provide the same ordering2647 guarantees as readsX() and writesX() respectively when accessing a2648 mapping with the default I/O attributes.2649 2650 (*) ioreadX(), iowriteX():2651 2652 These will perform appropriately for the type of access they're actually2653 doing, be it inX()/outX() or readX()/writeX().2654 2655With the exception of the string accessors (insX(), outsX(), readsX() and2656writesX()), all of the above assume that the underlying peripheral is2657little-endian and will therefore perform byte-swapping operations on big-endian2658architectures.2659 2660 2661========================================2662ASSUMED MINIMUM EXECUTION ORDERING MODEL2663========================================2664 2665It has to be assumed that the conceptual CPU is weakly-ordered but that it will2666maintain the appearance of program causality with respect to itself. Some CPUs2667(such as i386 or x86_64) are more constrained than others (such as powerpc or2668frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside2669of arch-specific code.2670 2671This means that it must be considered that the CPU will execute its instruction2672stream in any order it feels like - or even in parallel - provided that if an2673instruction in the stream depends on an earlier instruction, then that2674earlier instruction must be sufficiently complete[*] before the later2675instruction may proceed; in other words: provided that the appearance of2676causality is maintained.2677 2678 [*] Some instructions have more than one effect - such as changing the2679 condition codes, changing registers or changing memory - and different2680 instructions may depend on different effects.2681 2682A CPU may also discard any instruction sequence that winds up having no2683ultimate effect. For example, if two adjacent instructions both load an2684immediate value into the same register, the first may be discarded.2685 2686 2687Similarly, it has to be assumed that compiler might reorder the instruction2688stream in any way it sees fit, again provided the appearance of causality is2689maintained.2690 2691 2692============================2693THE EFFECTS OF THE CPU CACHE2694============================2695 2696The way cached memory operations are perceived across the system is affected to2697a certain extent by the caches that lie between CPUs and memory, and by the2698memory coherence system that maintains the consistency of state in the system.2699 2700As far as the way a CPU interacts with another part of the system through the2701caches goes, the memory system has to include the CPU's caches, and memory2702barriers for the most part act at the interface between the CPU and its cache2703(memory barriers logically act on the dotted line in the following diagram):2704 2705 <--- CPU ---> : <----------- Memory ----------->2706 :2707 +--------+ +--------+ : +--------+ +-----------+2708 | | | | : | | | | +--------+2709 | CPU | | Memory | : | CPU | | | | |2710 | Core |--->| Access |----->| Cache |<-->| | | |2711 | | | Queue | : | | | |--->| Memory |2712 | | | | : | | | | | |2713 +--------+ +--------+ : +--------+ | | | |2714 : | Cache | +--------+2715 : | Coherency |2716 : | Mechanism | +--------+2717 +--------+ +--------+ : +--------+ | | | |2718 | | | | : | | | | | |2719 | CPU | | Memory | : | CPU | | |--->| Device |2720 | Core |--->| Access |----->| Cache |<-->| | | |2721 | | | Queue | : | | | | | |2722 | | | | : | | | | +--------+2723 +--------+ +--------+ : +--------+ +-----------+2724 :2725 :2726 2727Although any particular load or store may not actually appear outside of the2728CPU that issued it since it may have been satisfied within the CPU's own cache,2729it will still appear as if the full memory access had taken place as far as the2730other CPUs are concerned since the cache coherency mechanisms will migrate the2731cacheline over to the accessing CPU and propagate the effects upon conflict.2732 2733The CPU core may execute instructions in any order it deems fit, provided the2734expected program causality appears to be maintained. Some of the instructions2735generate load and store operations which then go into the queue of memory2736accesses to be performed. The core may place these in the queue in any order2737it wishes, and continue execution until it is forced to wait for an instruction2738to complete.2739 2740What memory barriers are concerned with is controlling the order in which2741accesses cross from the CPU side of things to the memory side of things, and2742the order in which the effects are perceived to happen by the other observers2743in the system.2744 2745[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see2746their own loads and stores as if they had happened in program order.2747 2748[!] MMIO or other device accesses may bypass the cache system. This depends on2749the properties of the memory window through which devices are accessed and/or2750the use of any special device communication instructions the CPU may have.2751 2752 2753CACHE COHERENCY VS DMA2754----------------------2755 2756Not all systems maintain cache coherency with respect to devices doing DMA. In2757such cases, a device attempting DMA may obtain stale data from RAM because2758dirty cache lines may be resident in the caches of various CPUs, and may not2759have been written back to RAM yet. To deal with this, the appropriate part of2760the kernel must flush the overlapping bits of cache on each CPU (and maybe2761invalidate them as well).2762 2763In addition, the data DMA'd to RAM by a device may be overwritten by dirty2764cache lines being written back to RAM from a CPU's cache after the device has2765installed its own data, or cache lines present in the CPU's cache may simply2766obscure the fact that RAM has been updated, until at such time as the cacheline2767is discarded from the CPU's cache and reloaded. To deal with this, the2768appropriate part of the kernel must invalidate the overlapping bits of the2769cache on each CPU.2770 2771See Documentation/core-api/cachetlb.rst for more information on cache2772management.2773 2774 2775CACHE COHERENCY VS MMIO2776-----------------------2777 2778Memory mapped I/O usually takes place through memory locations that are part of2779a window in the CPU's memory space that has different properties assigned than2780the usual RAM directed window.2781 2782Amongst these properties is usually the fact that such accesses bypass the2783caching entirely and go directly to the device buses. This means MMIO accesses2784may, in effect, overtake accesses to cached memory that were emitted earlier.2785A memory barrier isn't sufficient in such a case, but rather the cache must be2786flushed between the cached memory write and the MMIO access if the two are in2787any way dependent.2788 2789 2790=========================2791THE THINGS CPUS GET UP TO2792=========================2793 2794A programmer might take it for granted that the CPU will perform memory2795operations in exactly the order specified, so that if the CPU is, for example,2796given the following piece of code to execute:2797 2798 a = READ_ONCE(*A);2799 WRITE_ONCE(*B, b);2800 c = READ_ONCE(*C);2801 d = READ_ONCE(*D);2802 WRITE_ONCE(*E, e);2803 2804they would then expect that the CPU will complete the memory operation for each2805instruction before moving on to the next one, leading to a definite sequence of2806operations as seen by external observers in the system:2807 2808 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.2809 2810 2811Reality is, of course, much messier. With many CPUs and compilers, the above2812assumption doesn't hold because:2813 2814 (*) loads are more likely to need to be completed immediately to permit2815 execution progress, whereas stores can often be deferred without a2816 problem;2817 2818 (*) loads may be done speculatively, and the result discarded should it prove2819 to have been unnecessary;2820 2821 (*) loads may be done speculatively, leading to the result having been fetched2822 at the wrong time in the expected sequence of events;2823 2824 (*) the order of the memory accesses may be rearranged to promote better use2825 of the CPU buses and caches;2826 2827 (*) loads and stores may be combined to improve performance when talking to2828 memory or I/O hardware that can do batched accesses of adjacent locations,2829 thus cutting down on transaction setup costs (memory and PCI devices may2830 both be able to do this); and2831 2832 (*) the CPU's data cache may affect the ordering, and while cache-coherency2833 mechanisms may alleviate this - once the store has actually hit the cache2834 - there's no guarantee that the coherency management will be propagated in2835 order to other CPUs.2836 2837So what another CPU, say, might actually observe from the above piece of code2838is:2839 2840 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B2841 2842 (Where "LOAD {*C,*D}" is a combined load)2843 2844 2845However, it is guaranteed that a CPU will be self-consistent: it will see its2846_own_ accesses appear to be correctly ordered, without the need for a memory2847barrier. For instance with the following code:2848 2849 U = READ_ONCE(*A);2850 WRITE_ONCE(*A, V);2851 WRITE_ONCE(*A, W);2852 X = READ_ONCE(*A);2853 WRITE_ONCE(*A, Y);2854 Z = READ_ONCE(*A);2855 2856and assuming no intervention by an external influence, it can be assumed that2857the final result will appear to be:2858 2859 U == the original value of *A2860 X == W2861 Z == Y2862 *A == Y2863 2864The code above may cause the CPU to generate the full sequence of memory2865accesses:2866 2867 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A2868 2869in that order, but, without intervention, the sequence may have almost any2870combination of elements combined or discarded, provided the program's view2871of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()2872are -not- optional in the above example, as there are architectures2873where a given CPU might reorder successive loads to the same location.2874On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is2875necessary to prevent this, for example, on Itanium the volatile casts2876used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq2877and st.rel instructions (respectively) that prevent such reordering.2878 2879The compiler may also combine, discard or defer elements of the sequence before2880the CPU even sees them.2881 2882For instance:2883 2884 *A = V;2885 *A = W;2886 2887may be reduced to:2888 2889 *A = W;2890 2891since, without either a write barrier or an WRITE_ONCE(), it can be2892assumed that the effect of the storage of V to *A is lost. Similarly:2893 2894 *A = Y;2895 Z = *A;2896 2897may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be2898reduced to:2899 2900 *A = Y;2901 Z = Y;2902 2903and the LOAD operation never appear outside of the CPU.2904 2905 2906AND THEN THERE'S THE ALPHA2907--------------------------2908 2909The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,2910some versions of the Alpha CPU have a split data cache, permitting them to have2911two semantically-related cache lines updated at separate times. This is where2912the address-dependency barrier really becomes necessary as this synchronises2913both caches with the memory coherence system, thus making it seem like pointer2914changes vs new data occur in the right order.2915 2916The Alpha defines the Linux kernel's memory model, although as of v4.152917the Linux kernel's addition of smp_mb() to READ_ONCE() on Alpha greatly2918reduced its impact on the memory model.2919 2920 2921VIRTUAL MACHINE GUESTS2922----------------------2923 2924Guests running within virtual machines might be affected by SMP effects even if2925the guest itself is compiled without SMP support. This is an artifact of2926interfacing with an SMP host while running an UP kernel. Using mandatory2927barriers for this use-case would be possible but is often suboptimal.2928 2929To handle this case optimally, low-level virt_mb() etc macros are available.2930These have the same effect as smp_mb() etc when SMP is enabled, but generate2931identical code for SMP and non-SMP systems. For example, virtual machine guests2932should use virt_mb() rather than smp_mb() when synchronizing against a2933(possibly SMP) host.2934 2935These are equivalent to smp_mb() etc counterparts in all other respects,2936in particular, they do not control MMIO effects: to control2937MMIO effects, use mandatory barriers.2938 2939 2940============2941EXAMPLE USES2942============2943 2944CIRCULAR BUFFERS2945----------------2946 2947Memory barriers can be used to implement circular buffering without the need2948of a lock to serialise the producer with the consumer. See:2949 2950 Documentation/core-api/circular-buffers.rst2951 2952for details.2953 2954 2955==========2956REFERENCES2957==========2958 2959Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,2960Digital Press)2961 Chapter 5.2: Physical Address Space Characteristics2962 Chapter 5.4: Caches and Write Buffers2963 Chapter 5.5: Data Sharing2964 Chapter 5.6: Read/Write Ordering2965 2966AMD64 Architecture Programmer's Manual Volume 2: System Programming2967 Chapter 7.1: Memory-Access Ordering2968 Chapter 7.4: Buffering and Combining Memory Writes2969 2970ARM Architecture Reference Manual (ARMv8, for ARMv8-A architecture profile)2971 Chapter B2: The AArch64 Application Level Memory Model2972 2973IA-32 Intel Architecture Software Developer's Manual, Volume 3:2974System Programming Guide2975 Chapter 7.1: Locked Atomic Operations2976 Chapter 7.2: Memory Ordering2977 Chapter 7.4: Serializing Instructions2978 2979The SPARC Architecture Manual, Version 92980 Chapter 8: Memory Models2981 Appendix D: Formal Specification of the Memory Models2982 Appendix J: Programming with the Memory Models2983 2984Storage in the PowerPC (Stone and Fitzgerald)2985 2986UltraSPARC Programmer Reference Manual2987 Chapter 5: Memory Accesses and Cacheability2988 Chapter 15: Sparc-V9 Memory Models2989 2990UltraSPARC III Cu User's Manual2991 Chapter 9: Memory Models2992 2993UltraSPARC IIIi Processor User's Manual2994 Chapter 8: Memory Models2995 2996UltraSPARC Architecture 20052997 Chapter 9: Memory2998 Appendix D: Formal Specifications of the Memory Models2999 3000UltraSPARC T1 Supplement to the UltraSPARC Architecture 20053001 Chapter 8: Memory Models3002 Appendix F: Caches and Cache Coherency3003 3004Solaris Internals, Core Kernel Architecture, p63-68:3005 Chapter 3.3: Hardware Considerations for Locks and3006 Synchronization3007 3008Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching3009for Kernel Programmers:3010 Chapter 13: Other Memory Models3011 3012Intel Itanium Architecture Software Developer's Manual: Volume 1:3013 Section 2.6: Speculation3014 Section 4.4: Memory Access3015