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SPDX-License-Identifier: GPL-2.02.. include:: <isonum.txt>3 4======================================================5Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop)6======================================================7 8Controller Register Map9-----------------------10 11For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR212 13 ============== ==================================14 BAR0 offset Register15 ============== ==================================16 0x11C5C Link Interface IRQ Set17 0x11C60 Link Interface IRQ Clear18 ============== ==================================19 20 ============== ==================================21 BAR2 offset Register22 ============== ==================================23 0x10 Inbound Message Register 024 0x14 Inbound Message Register 125 0x18 Outbound Message Register 026 0x1C Outbound Message Register 127 0x20 Inbound Doorbell Register28 0x24 Inbound Interrupt Status Register29 0x28 Inbound Interrupt Mask Register30 0x30 Outbound Interrupt Status Register31 0x34 Outbound Interrupt Mask Register32 0x40 Inbound Queue Port33 0x44 Outbound Queue Port34 ============== ==================================35 36For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:37 38 ============== ==================================39 BAR0 offset Register40 ============== ==================================41 0x10 Inbound Message Register 042 0x14 Inbound Message Register 143 0x18 Outbound Message Register 044 0x1C Outbound Message Register 145 0x20 Inbound Doorbell Register46 0x24 Inbound Interrupt Status Register47 0x28 Inbound Interrupt Mask Register48 0x30 Outbound Interrupt Status Register49 0x34 Outbound Interrupt Mask Register50 0x40 Inbound Queue Port51 0x44 Outbound Queue Port52 ============== ==================================53 54For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:55 56 ============== ==================================57 BAR0 offset Register58 ============== ==================================59 0x20400 Inbound Doorbell Register60 0x20404 Inbound Interrupt Mask Register61 0x20408 Outbound Doorbell Register62 0x2040C Outbound Interrupt Mask Register63 ============== ==================================64 65 ============== ==================================66 BAR1 offset Register67 ============== ==================================68 0x0 Inbound Queue Head Pointer69 0x4 Inbound Queue Tail Pointer70 0x8 Outbound Queue Head Pointer71 0xC Outbound Queue Tail Pointer72 0x10 Inbound Message Register73 0x14 Outbound Message Register74 0x40-0x1040 Inbound Queue75 0x1040-0x2040 Outbound Queue76 ============== ==================================77 78For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:79 80 ============== ==================================81 BAR0 offset Register82 ============== ==================================83 0x0 IOP configuration information.84 ============== ==================================85 86 ============== ===================================================87 BAR1 offset Register88 ============== ===================================================89 0x4000 Inbound List Base Address Low90 0x4004 Inbound List Base Address High91 0x4018 Inbound List Write Pointer92 0x402C Inbound List Configuration and Control93 0x4050 Outbound List Base Address Low94 0x4054 Outbound List Base Address High95 0x4058 Outbound List Copy Pointer Shadow Base Address Low96 0x405C Outbound List Copy Pointer Shadow Base Address High97 0x4088 Outbound List Interrupt Cause98 0x408C Outbound List Interrupt Enable99 0x1020C PCIe Function 0 Interrupt Enable100 0x10400 PCIe Function 0 to CPU Message A101 0x10420 CPU to PCIe Function 0 Message A102 0x10480 CPU to PCIe Function 0 Doorbell103 0x10484 CPU to PCIe Function 0 Doorbell Enable104 ============== ===================================================105 106 107I/O Request Workflow of Not Marvell Frey108----------------------------------------109 110All queued requests are handled via inbound/outbound queue port.111A request packet can be allocated in either IOP or host memory.112 113To send a request to the controller:114 115 - Get a free request packet by reading the inbound queue port or116 allocate a free request in host DMA coherent memory.117 118 The value returned from the inbound queue port is an offset119 relative to the IOP BAR0.120 121 Requests allocated in host memory must be aligned on 32-bytes boundary.122 123 - Fill the packet.124 125 - Post the packet to IOP by writing it to inbound queue. For requests126 allocated in IOP memory, write the offset to inbound queue port. For127 requests allocated in host memory, write (0x80000000|(bus_addr>>5))128 to the inbound queue port.129 130 - The IOP process the request. When the request is completed, it131 will be put into outbound queue. An outbound interrupt will be132 generated.133 134 For requests allocated in IOP memory, the request offset is posted to135 outbound queue.136 137 For requests allocated in host memory, (0x80000000|(bus_addr>>5))138 is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT139 flag is set in the request, the low 32-bit context value will be140 posted instead.141 142 - The host read the outbound queue and complete the request.143 144 For requests allocated in IOP memory, the host driver free the request145 by writing it to the outbound queue.146 147Non-queued requests (reset/flush etc) can be sent via inbound message148register 0. An outbound message with the same value indicates the completion149of an inbound message.150 151 152I/O Request Workflow of Marvell Frey153------------------------------------154 155All queued requests are handled via inbound/outbound list.156 157To send a request to the controller:158 159 - Allocate a free request in host DMA coherent memory.160 161 Requests allocated in host memory must be aligned on 32-bytes boundary.162 163 - Fill the request with index of the request in the flag.164 165 Fill a free inbound list unit with the physical address and the size of166 the request.167 168 Set up the inbound list write pointer with the index of previous unit,169 round to 0 if the index reaches the supported count of requests.170 171 - Post the inbound list writer pointer to IOP.172 173 - The IOP process the request. When the request is completed, the flag of174 the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a175 free outbound list unit and the index of the outbound list unit will be176 put into the copy pointer shadow register. An outbound interrupt will be177 generated.178 179 - The host read the outbound list copy pointer shadow register and compare180 with previous saved read pointer N. If they are different, the host will181 read the (N+1)th outbound list unit.182 183 The host get the index of the request from the (N+1)th outbound list184 unit and complete the request.185 186Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe187Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register188with the same value indicates the completion of message.189 190 191User-level Interface192---------------------193 194The driver exposes following sysfs attributes:195 196 ================== === ========================197 NAME R/W Description198 ================== === ========================199 driver-version R driver version string200 firmware-version R firmware version string201 ================== === ========================202 203 204-----------------------------------------------------------------------------205 206Copyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.207 208 This file is distributed in the hope that it will be useful,209 but WITHOUT ANY WARRANTY; without even the implied warranty of210 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the211 GNU General Public License for more details.212 213 linux@highpoint-tech.com214 215 http://www.highpoint-tech.com216