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1==============================================2spi_lm70llp : LM70-LLP parport-to-SPI adapter3==============================================4 5Supported board/chip:6 7 * National Semiconductor LM70 LLP evaluation board8 9 Datasheet: https://www.ti.com/lit/gpn/lm7010 11Author:12 Kaiwan N Billimoria <kaiwan@designergraphix.com>13 14Description15-----------16This driver provides glue code connecting a National Semiconductor LM70 LLP17temperature sensor evaluation board to the kernel's SPI core subsystem.18 19This is a SPI master controller driver. It can be used in conjunction with20(layered under) the LM70 logical driver (a "SPI protocol driver").21In effect, this driver turns the parallel port interface on the eval board22into a SPI bus with a single device, which will be driven by the generic23LM70 driver (drivers/hwmon/lm70.c).24 25 26Hardware Interfacing27--------------------28The schematic for this particular board (the LM70EVAL-LLP) is29available (on page 4) here:30 31 https://download.datasheets.com/pdfs/documentation/nat/kit&board/lm70llpevalmanual.pdf32 33The hardware interfacing on the LM70 LLP eval board is as follows:34 35 ======== == ========= ==========36 Parallel LM70 LLP37 Port . Direction JP2 Header38 ======== == ========= ==========39 D0 2 - -40 D1 3 --> V+ 541 D2 4 --> V+ 542 D3 5 --> V+ 543 D4 6 --> V+ 544 D5 7 --> nCS 845 D6 8 --> SCLK 346 D7 9 --> SI/O 547 GND 25 - GND 748 Select 13 <-- SI/O 149 ======== == ========= ==========50 51Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin52is connected to both pin D7 (as Master Out) and Select (as Master In)53using an arrangement that lets either the parport or the LM70 pull the54pin low. This can't be shared with true SPI devices, but other 3-wire55devices might share the same SI/SO pin.56 57The bitbanger routine in this driver (lm70_txrx) is called back from58the bound "hwmon/lm70" protocol driver through its sysfs hook, using a59spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging.60The lm70 driver then interprets the resulting digital temperature value61and exports it through sysfs.62 63A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic64shows that the SI/O line from the LM70 chip is connected to the base of a65transistor Q1 (and also a pullup, and a zener diode to D7); while the66collector is tied to VCC.67 68Interpreting this circuit, when the LM70 SI/O line is High (or tristate69and not grounded by the host via D7), the transistor conducts and switches70the collector to zero, which is reflected on pin 13 of the DB25 parport71connector. When SI/O is Low (driven by the LM70 or the host) on the other72hand, the transistor is cut off and the voltage tied to its collector is73reflected on pin 13 as a High level.74 75So: the getmiso inline routine in this driver takes this fact into account,76inverting the value read at pin 13.77 78 79Thanks to80---------81 82- David Brownell for mentoring the SPI-side driver development.83- Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.84- Nadir Billimoria for help interpreting the circuit schematic.85