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1======================================2Coresight - HW Assisted Tracing on ARM3======================================4 5 :Author: Mathieu Poirier <mathieu.poirier@linaro.org>6 :Date: September 11th, 20147 8Introduction9------------10 11Coresight is an umbrella of technologies allowing for the debugging of ARM12based SoC. It includes solutions for JTAG and HW assisted tracing. This13document is concerned with the latter.14 15HW assisted tracing is becoming increasingly useful when dealing with systems16that have many SoCs and other components like GPU and DMA engines. ARM has17developed a HW assisted tracing solution by means of different components, each18being added to a design at synthesis time to cater to specific tracing needs.19Components are generally categorised as source, link and sinks and are20(usually) discovered using the AMBA bus.21 22"Sources" generate a compressed stream representing the processor instruction23path based on tracing scenarios as configured by users. From there the stream24flows through the coresight system (via ATB bus) using links that are connecting25the emanating source to a sink(s). Sinks serve as endpoints to the coresight26implementation, either storing the compressed stream in a memory buffer or27creating an interface to the outside world where data can be transferred to a28host without fear of filling up the onboard coresight memory buffer.29 30At typical coresight system would look like this::31 32 *****************************************************************33 **************************** AMBA AXI ****************************===||34 ***************************************************************** ||35 ^ ^ | ||36 | | * **37 0000000 ::::: 0000000 ::::: ::::: @@@@@@@ ||||||||||||38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||41 | # ETM # ::::: | # PTM # ::::: ::::: @ |42 | ##### ^ ^ | ##### ^ ! ^ ! . | |||||||||43 | |->### | ! | |->### | ! | ! . | || DAP ||44 | | # | ! | | # | ! | ! . | |||||||||45 | | . | ! | | . | ! | ! . | | |46 | | . | ! | | . | ! | ! . | | *47 | | . | ! | | . | ! | ! . | | SWD/48 | | . | ! | | . | ! | ! . | | JTAG49 *****************************************************************<-|50 *************************** AMBA Debug APB ************************51 *****************************************************************52 | . ! . ! ! . |53 | . * . * * . |54 *****************************************************************55 ******************** Cross Trigger Matrix (CTM) *******************56 *****************************************************************57 | . ^ . . |58 | * ! * * |59 *****************************************************************60 ****************** AMBA Advanced Trace Bus (ATB) ******************61 *****************************************************************62 | ! =============== |63 | * ===== F =====<---------|64 | ::::::::: ==== U ====65 |-->:: CTI ::<!! === N ===66 | ::::::::: ! == N ==67 | ^ * == E ==68 | ! &&&&&&&&& IIIIIII == L ==69 |------>&& ETB &&<......II I =======70 | ! &&&&&&&&& II I .71 | ! I I .72 | ! I REP I<..........73 | ! I I74 | !!>&&&&&&&&& II I *Source: ARM ltd.75 |------>& TPIU &<......II I DAP = Debug Access Port76 &&&&&&&&& IIIIIII ETM = Embedded Trace Macrocell77 ; PTM = Program Trace Macrocell78 ; CTI = Cross Trigger Interface79 * ETB = Embedded Trace Buffer80 To trace port TPIU= Trace Port Interface Unit81 SWD = Serial Wire Debug82 83While on target configuration of the components is done via the APB bus,84all trace data are carried out-of-band on the ATB bus. The CTM provides85a way to aggregate and distribute signals between CoreSight components.86 87The coresight framework provides a central point to represent, configure and88manage coresight devices on a platform. This first implementation centers on89the basic tracing functionality, enabling components such ETM/PTM, funnel,90replicator, TMC, TPIU and ETB. Future work will enable more91intricate IP blocks such as STM and CTI.92 93 94Acronyms and Classification95---------------------------96 97Acronyms:98 99PTM:100 Program Trace Macrocell101ETM:102 Embedded Trace Macrocell103STM:104 System trace Macrocell105ETB:106 Embedded Trace Buffer107ITM:108 Instrumentation Trace Macrocell109TPIU:110 Trace Port Interface Unit111TMC-ETR:112 Trace Memory Controller, configured as Embedded Trace Router113TMC-ETF:114 Trace Memory Controller, configured as Embedded Trace FIFO115CTI:116 Cross Trigger Interface117 118Classification:119 120Source:121 ETMv3.x ETMv4, PTMv1.0, PTMv1.1, STM, STM500, ITM122Link:123 Funnel, replicator (intelligent or not), TMC-ETR124Sinks:125 ETBv1.0, ETB1.1, TPIU, TMC-ETF126Misc:127 CTI128 129 130Device Tree Bindings131--------------------132 133See ``Documentation/devicetree/bindings/arm/arm,coresight-*.yaml`` for details.134 135As of this writing drivers for ITM, STMs and CTIs are not provided but are136expected to be added as the solution matures.137 138 139Framework and implementation140----------------------------141 142The coresight framework provides a central point to represent, configure and143manage coresight devices on a platform. Any coresight compliant device can144register with the framework for as long as they use the right APIs:145 146.. c:function:: struct coresight_device *coresight_register(struct coresight_desc *desc);147.. c:function:: void coresight_unregister(struct coresight_device *csdev);148 149The registering function is taking a ``struct coresight_desc *desc`` and150register the device with the core framework. The unregister function takes151a reference to a ``struct coresight_device *csdev`` obtained at registration time.152 153If everything goes well during the registration process the new devices will154show up under /sys/bus/coresight/devices, as showns here for a TC2 platform::155 156 root:~# ls /sys/bus/coresight/devices/157 replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm158 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm159 root:~#160 161The functions take a ``struct coresight_device``, which looks like this::162 163 struct coresight_desc {164 enum coresight_dev_type type;165 struct coresight_dev_subtype subtype;166 const struct coresight_ops *ops;167 struct coresight_platform_data *pdata;168 struct device *dev;169 const struct attribute_group **groups;170 };171 172 173The "coresight_dev_type" identifies what the device is, i.e, source link or174sink while the "coresight_dev_subtype" will characterise that type further.175 176The ``struct coresight_ops`` is mandatory and will tell the framework how to177perform base operations related to the components, each component having178a different set of requirement. For that ``struct coresight_ops_sink``,179``struct coresight_ops_link`` and ``struct coresight_ops_source`` have been180provided.181 182The next field ``struct coresight_platform_data *pdata`` is acquired by calling183``of_get_coresight_platform_data()``, as part of the driver's _probe routine and184``struct device *dev`` gets the device reference embedded in the ``amba_device``::185 186 static int etm_probe(struct amba_device *adev, const struct amba_id *id)187 {188 ...189 ...190 drvdata->dev = &adev->dev;191 ...192 }193 194Specific class of device (source, link, or sink) have generic operations195that can be performed on them (see ``struct coresight_ops``). The ``**groups``196is a list of sysfs entries pertaining to operations197specific to that component only. "Implementation defined" customisations are198expected to be accessed and controlled using those entries.199 200Device Naming scheme201--------------------202 203The devices that appear on the "coresight" bus were named the same as their204parent devices, i.e, the real devices that appears on AMBA bus or the platform bus.205Thus the names were based on the Linux Open Firmware layer naming convention,206which follows the base physical address of the device followed by the device207type. e.g::208 209 root:~# ls /sys/bus/coresight/devices/210 20010000.etf 20040000.funnel 20100000.stm 22040000.etm211 22140000.etm 230c0000.funnel 23240000.etm 20030000.tpiu212 20070000.etr 20120000.replicator 220c0000.funnel213 23040000.etm 23140000.etm 23340000.etm214 215However, with the introduction of ACPI support, the names of the real216devices are a bit cryptic and non-obvious. Thus, a new naming scheme was217introduced to use more generic names based on the type of the device. The218following rules apply::219 220 1) Devices that are bound to CPUs, are named based on the CPU logical221 number.222 223 e.g, ETM bound to CPU0 is named "etm0"224 225 2) All other devices follow a pattern, "<device_type_prefix>N", where :226 227 <device_type_prefix> - A prefix specific to the type of the device228 N - a sequential number assigned based on the order229 of probing.230 231 e.g, tmc_etf0, tmc_etr0, funnel0, funnel1232 233Thus, with the new scheme the devices could appear as ::234 235 root:~# ls /sys/bus/coresight/devices/236 etm0 etm1 etm2 etm3 etm4 etm5 funnel0237 funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0238 239Some of the examples below might refer to old naming scheme and some240to the newer scheme, to give a confirmation that what you see on your241system is not unexpected. One must use the "names" as they appear on242the system under specified locations.243 244Topology Representation245-----------------------246 247Each CoreSight component has a ``connections`` directory which will contain248links to other CoreSight components. This allows the user to explore the trace249topology and for larger systems, determine the most appropriate sink for a250given source. The connection information can also be used to establish251which CTI devices are connected to a given component. This directory contains a252``nr_links`` attribute detailing the number of links in the directory.253 254For an ETM source, in this case ``etm0`` on a Juno platform, a typical255arrangement will be::256 257 linaro-developer:~# ls - l /sys/bus/coresight/devices/etm0/connections258 <file details> cti_cpu0 -> ../../../23020000.cti/cti_cpu0259 <file details> nr_links260 <file details> out:0 -> ../../../230c0000.funnel/funnel2261 262Following the out port to ``funnel2``::263 264 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel2/connections265 <file details> in:0 -> ../../../23040000.etm/etm0266 <file details> in:1 -> ../../../23140000.etm/etm3267 <file details> in:2 -> ../../../23240000.etm/etm4268 <file details> in:3 -> ../../../23340000.etm/etm5269 <file details> nr_links270 <file details> out:0 -> ../../../20040000.funnel/funnel0271 272And again to ``funnel0``::273 274 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel0/connections275 <file details> in:0 -> ../../../220c0000.funnel/funnel1276 <file details> in:1 -> ../../../230c0000.funnel/funnel2277 <file details> nr_links278 <file details> out:0 -> ../../../20010000.etf/tmc_etf0279 280Finding the first sink ``tmc_etf0``. This can be used to collect data281as a sink, or as a link to propagate further along the chain::282 283 linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etf0/connections284 <file details> cti_sys0 -> ../../../20020000.cti/cti_sys0285 <file details> in:0 -> ../../../20040000.funnel/funnel0286 <file details> nr_links287 <file details> out:0 -> ../../../20150000.funnel/funnel4288 289via ``funnel4``::290 291 linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel4/connections292 <file details> in:0 -> ../../../20010000.etf/tmc_etf0293 <file details> in:1 -> ../../../20140000.etf/tmc_etf1294 <file details> nr_links295 <file details> out:0 -> ../../../20120000.replicator/replicator0296 297and a ``replicator0``::298 299 linaro-developer:~# ls -l /sys/bus/coresight/devices/replicator0/connections300 <file details> in:0 -> ../../../20150000.funnel/funnel4301 <file details> nr_links302 <file details> out:0 -> ../../../20030000.tpiu/tpiu0303 <file details> out:1 -> ../../../20070000.etr/tmc_etr0304 305Arriving at the final sink in the chain, ``tmc_etr0``::306 307 linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etr0/connections308 <file details> cti_sys0 -> ../../../20020000.cti/cti_sys0309 <file details> in:0 -> ../../../20120000.replicator/replicator0310 <file details> nr_links311 312As described below, when using sysfs it is sufficient to enable a sink and313a source for successful trace. The framework will correctly enable all314intermediate links as required.315 316Note: ``cti_sys0`` appears in two of the connections lists above.317CTIs can connect to multiple devices and are arranged in a star topology318via the CTM. See (Documentation/trace/coresight/coresight-ect.rst)319[#fourth]_ for further details.320Looking at this device we see 4 connections::321 322 linaro-developer:~# ls -l /sys/bus/coresight/devices/cti_sys0/connections323 <file details> nr_links324 <file details> stm0 -> ../../../20100000.stm/stm0325 <file details> tmc_etf0 -> ../../../20010000.etf/tmc_etf0326 <file details> tmc_etr0 -> ../../../20070000.etr/tmc_etr0327 <file details> tpiu0 -> ../../../20030000.tpiu/tpiu0328 329 330How to use the tracer modules331-----------------------------332 333There are two ways to use the Coresight framework:334 3351. using the perf cmd line tools.3362. interacting directly with the Coresight devices using the sysFS interface.337 338Preference is given to the former as using the sysFS interface339requires a deep understanding of the Coresight HW. The following sections340provide details on using both methods.341 342Using the sysFS interface343~~~~~~~~~~~~~~~~~~~~~~~~~344 345Before trace collection can start, a coresight sink needs to be identified.346There is no limit on the amount of sinks (nor sources) that can be enabled at347any given moment. As a generic operation, all device pertaining to the sink348class will have an "active" entry in sysfs::349 350 root:/sys/bus/coresight/devices# ls351 replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm352 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm353 root:/sys/bus/coresight/devices# ls 20010000.etb354 enable_sink status trigger_cntr355 root:/sys/bus/coresight/devices# echo 1 > 20010000.etb/enable_sink356 root:/sys/bus/coresight/devices# cat 20010000.etb/enable_sink357 1358 root:/sys/bus/coresight/devices#359 360At boot time the current etm3x driver will configure the first address361comparator with "_stext" and "_etext", essentially tracing any instruction362that falls within that range. As such "enabling" a source will immediately363trigger a trace capture::364 365 root:/sys/bus/coresight/devices# echo 1 > 2201c000.ptm/enable_source366 root:/sys/bus/coresight/devices# cat 2201c000.ptm/enable_source367 1368 root:/sys/bus/coresight/devices# cat 20010000.etb/status369 Depth: 0x2000370 Status: 0x1371 RAM read ptr: 0x0372 RAM wrt ptr: 0x19d3 <----- The write pointer is moving373 Trigger cnt: 0x0374 Control: 0x1375 Flush status: 0x0376 Flush ctrl: 0x2001377 root:/sys/bus/coresight/devices#378 379Trace collection is stopped the same way::380 381 root:/sys/bus/coresight/devices# echo 0 > 2201c000.ptm/enable_source382 root:/sys/bus/coresight/devices#383 384The content of the ETB buffer can be harvested directly from /dev::385 386 root:/sys/bus/coresight/devices# dd if=/dev/20010000.etb \387 of=~/cstrace.bin388 64+0 records in389 64+0 records out390 32768 bytes (33 kB) copied, 0.00125258 s, 26.2 MB/s391 root:/sys/bus/coresight/devices#392 393The file cstrace.bin can be decompressed using "ptm2human", DS-5 or Trace32.394 395Following is a DS-5 output of an experimental loop that increments a variable up396to a certain value. The example is simple and yet provides a glimpse of the397wealth of possibilities that coresight provides.398::399 400 Info Tracing enabled401 Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}402 Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc403 Instruction 0 0x8026B544 E3A03000 false MOV r3,#0404 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]405 Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]406 Instruction 0 0x8026B550 E3530004 false CMP r3,#4407 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1408 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]409 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c410 Timestamp Timestamp: 17106715833411 Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4]412 Instruction 0 0x8026B550 E3530004 false CMP r3,#4413 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1414 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]415 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c416 Instruction 9 0x8026B54C E59D3004 false LDR r3,[sp,#4]417 Instruction 0 0x8026B550 E3530004 false CMP r3,#4418 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1419 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]420 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c421 Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]422 Instruction 0 0x8026B550 E3530004 false CMP r3,#4423 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1424 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]425 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c426 Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]427 Instruction 0 0x8026B550 E3530004 false CMP r3,#4428 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1429 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]430 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c431 Instruction 10 0x8026B54C E59D3004 false LDR r3,[sp,#4]432 Instruction 0 0x8026B550 E3530004 false CMP r3,#4433 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1434 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]435 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c436 Instruction 6 0x8026B560 EE1D3F30 false MRC p15,#0x0,r3,c13,c0,#1437 Instruction 0 0x8026B564 E1A0100D false MOV r1,sp438 Instruction 0 0x8026B568 E3C12D7F false BIC r2,r1,#0x1fc0439 Instruction 0 0x8026B56C E3C2203F false BIC r2,r2,#0x3f440 Instruction 0 0x8026B570 E59D1004 false LDR r1,[sp,#4]441 Instruction 0 0x8026B574 E59F0010 false LDR r0,[pc,#16] ; [0x8026B58C] = 0x80550368442 Instruction 0 0x8026B578 E592200C false LDR r2,[r2,#0xc]443 Instruction 0 0x8026B57C E59221D0 false LDR r2,[r2,#0x1d0]444 Instruction 0 0x8026B580 EB07A4CF true BL {pc}+0x1e9344 ; 0x804548c4445 Info Tracing enabled446 Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc447 Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc}448 Timestamp Timestamp: 17107041535449 450Using perf framework451~~~~~~~~~~~~~~~~~~~~452 453Coresight tracers are represented using the Perf framework's Performance454Monitoring Unit (PMU) abstraction. As such the perf framework takes charge of455controlling when tracing gets enabled based on when the process of interest is456scheduled. When configured in a system, Coresight PMUs will be listed when457queried by the perf command line tool:458 459 linaro@linaro-nano:~$ ./perf list pmu460 461 List of pre-defined events (to be used in -e):462 463 cs_etm// [Kernel PMU event]464 465 linaro@linaro-nano:~$466 467Regardless of the number of tracers available in a system (usually equal to the468amount of processor cores), the "cs_etm" PMU will be listed only once.469 470A Coresight PMU works the same way as any other PMU, i.e the name of the PMU is471listed along with configuration options within forward slashes '/'. Since a472Coresight system will typically have more than one sink, the name of the sink to473work with needs to be specified as an event option.474On newer kernels the available sinks are listed in sysFS under475($SYSFS)/bus/event_source/devices/cs_etm/sinks/::476 477 root@localhost:/sys/bus/event_source/devices/cs_etm/sinks# ls478 tmc_etf0 tmc_etr0 tpiu0479 480On older kernels, this may need to be found from the list of coresight devices,481available under ($SYSFS)/bus/coresight/devices/::482 483 root:~# ls /sys/bus/coresight/devices/484 etm0 etm1 etm2 etm3 etm4 etm5 funnel0485 funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0486 root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread program487 488As mentioned above in section "Device Naming scheme", the names of the devices could489look different from what is used in the example above. One must use the device names490as it appears under the sysFS.491 492The syntax within the forward slashes '/' is important. The '@' character493tells the parser that a sink is about to be specified and that this is the sink494to use for the trace session.495 496More information on the above and other example on how to use Coresight with497the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub498repository [#third]_.499 500Advanced perf framework usage501-----------------------------502 503AutoFDO analysis using the perf tools504~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~505 506perf can be used to record and analyze trace of programs.507 508Execution can be recorded using 'perf record' with the cs_etm event,509specifying the name of the sink to record to, e.g::510 511 perf record -e cs_etm/@tmc_etr0/u --per-thread512 513The 'perf report' and 'perf script' commands can be used to analyze execution,514synthesizing instruction and branch events from the instruction trace.515'perf inject' can be used to replace the trace data with the synthesized events.516The --itrace option controls the type and frequency of synthesized events517(see perf documentation).518 519Note that only 64-bit programs are currently supported - further work is520required to support instruction decode of 32-bit Arm programs.521 522Tracing PID523~~~~~~~~~~~524 525The kernel can be built to write the PID value into the PE ContextID registers.526For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may527implement Arm Virtualization Host Extensions (VHE), which the kernel can528run at EL2 as a virtualisation host; in this case, the PID value is stored in529CONTEXTIDR_EL2.530 531perf provides PMU formats that program the ETM to insert these values into the532trace data; the PMU formats are defined as below:533 534 "contextid1": Available on both EL1 kernel and EL2 kernel. When the535 kernel is running at EL1, "contextid1" enables the PID536 tracing; when the kernel is running at EL2, this enables537 tracing the PID of guest applications.538 539 "contextid2": Only usable when the kernel is running at EL2. When540 selected, enables PID tracing on EL2 kernel.541 542 "contextid": Will be an alias for the option that enables PID543 tracing. I.e,544 contextid == contextid1, on EL1 kernel.545 contextid == contextid2, on EL2 kernel.546 547perf will always enable PID tracing at the relevant EL, this is accomplished by548automatically enable the "contextid" config - but for EL2 it is possible to make549specific adjustments using configs "contextid1" and "contextid2", E.g. if a user550wants to trace PIDs for both host and guest, the two configs "contextid1" and551"contextid2" can be set at the same time:552 553 perf record -e cs_etm/contextid1,contextid2/u -- vm554 555 556Generating coverage files for Feedback Directed Optimization: AutoFDO557~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~558 559'perf inject' accepts the --itrace option in which case tracing data is560removed and replaced with the synthesized events. e.g.561::562 563 perf inject --itrace --strip -i perf.data -o perf.data.new564 565Below is an example of using ARM ETM for autoFDO. It requires autofdo566(https://github.com/google/autofdo) and gcc version 5. The bubble567sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial).568::569 570 $ gcc-5 -O3 sort.c -o sort571 $ taskset -c 2 ./sort572 Bubble sorting array of 30000 elements573 5910 ms574 575 $ perf record -e cs_etm/@tmc_etr0/u --per-thread taskset -c 2 ./sort576 Bubble sorting array of 30000 elements577 12543 ms578 [ perf record: Woken up 35 times to write data ]579 [ perf record: Captured and wrote 69.640 MB perf.data ]580 581 $ perf inject -i perf.data -o inj.data --itrace=il64 --strip582 $ create_gcov --binary=./sort --profile=inj.data --gcov=sort.gcov -gcov_version=1583 $ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo584 $ taskset -c 2 ./sort_autofdo585 Bubble sorting array of 30000 elements586 5806 ms587 588Config option formats589~~~~~~~~~~~~~~~~~~~~~590 591The following strings can be provided between // on the perf command line to enable various options.592They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/593 594.. list-table::595 :header-rows: 1596 597 * - Option598 - Description599 * - branch_broadcast600 - Session local version of the system wide setting:601 :ref:`ETM_MODE_BB <coresight-branch-broadcast>`602 * - contextid603 - See `Tracing PID`_604 * - contextid1605 - See `Tracing PID`_606 * - contextid2607 - See `Tracing PID`_608 * - configid609 - Selection for a custom configuration. This is an implementation detail and not used directly,610 see :ref:`trace/coresight/coresight-config:Using Configurations in perf`611 * - preset612 - Override for parameters in a custom configuration, see613 :ref:`trace/coresight/coresight-config:Using Configurations in perf`614 * - sinkid615 - Hashed version of the string to select a sink, automatically set when using the @ notation.616 This is an internal implementation detail and is not used directly, see `Using perf617 framework`_.618 * - cycacc619 - Session local version of the system wide setting: :ref:`ETMv4_MODE_CYCACC620 <coresight-cycle-accurate>`621 * - retstack622 - Session local version of the system wide setting: :ref:`ETM_MODE_RETURNSTACK623 <coresight-return-stack>`624 * - timestamp625 - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP626 <coresight-timestamp>`627 * - cc_threshold628 - Cycle count threshold value. If nothing is provided here or the provided value is 0, then the629 default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold630 value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead.631 632How to use the STM module633-------------------------634 635Using the System Trace Macrocell module is the same as the tracers - the only636difference is that clients are driving the trace capture rather637than the program flow through the code.638 639As with any other CoreSight component, specifics about the STM tracer can be640found in sysfs with more information on each entry being found in [#first]_::641 642 root@genericarmv8:~# ls /sys/bus/coresight/devices/stm0643 enable_source hwevent_select port_enable subsystem uevent644 hwevent_enable mgmt port_select traceid645 root@genericarmv8:~#646 647Like any other source a sink needs to be identified and the STM enabled before648being used::649 650 root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink651 root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/stm0/enable_source652 653From there user space applications can request and use channels using the devfs654interface provided for that purpose by the generic STM API::655 656 root@genericarmv8:~# ls -l /dev/stm0657 crw------- 1 root root 10, 61 Jan 3 18:11 /dev/stm0658 root@genericarmv8:~#659 660Details on how to use the generic STM API can be found here:661- Documentation/trace/stm.rst [#second]_.662 663The CTI & CTM Modules664---------------------665 666The CTI (Cross Trigger Interface) provides a set of trigger signals between667individual CTIs and components, and can propagate these between all CTIs via668channels on the CTM (Cross Trigger Matrix).669 670A separate documentation file is provided to explain the use of these devices.671(Documentation/trace/coresight/coresight-ect.rst) [#fourth]_.672 673CoreSight System Configuration674------------------------------675 676CoreSight components can be complex devices with many programming options.677Furthermore, components can be programmed to interact with each other across the678complete system.679 680A CoreSight System Configuration manager is provided to allow these complex programming681configurations to be selected and used easily from perf and sysfs.682 683See the separate document for further information.684(Documentation/trace/coresight/coresight-config.rst) [#fifth]_.685 686 687.. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm688 689.. [#second] Documentation/trace/stm.rst690 691.. [#third] https://github.com/Linaro/perf-opencsd692 693.. [#fourth] Documentation/trace/coresight/coresight-ect.rst694 695.. [#fifth] Documentation/trace/coresight/coresight-config.rst696