55 lines · plain
1.. SPDX-License-Identifier: GPL-2.0-or-later2 3=====================4Kernel driver w1-uart5=====================6 7Author: Christoph Winklhofer <cj.winklhofer@gmail.com>8 9 10Description11-----------12 13UART 1-Wire bus driver. The driver utilizes the UART interface via the14Serial Device Bus to create the 1-Wire timing patterns as described in15the document `"Using a UART to Implement a 1-Wire Bus Master"`_.16 17.. _"Using a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html18 19In short, the UART peripheral must support full-duplex and operate in20open-drain mode. The timing patterns are generated by a specific21combination of baud-rate and transmitted byte, which corresponds to a221-Wire read bit, write bit or reset pulse.23 24For instance the timing pattern for a 1-Wire reset and presence detect uses25the baud-rate 9600, i.e. 104.2 us per bit. The transmitted byte 0xf0 over26UART (least significant bit first, start-bit low) sets the reset low time27for 1-Wire to 521 us. A present 1-Wire device changes the received byte by28pulling the line low, which is used by the driver to evaluate the result of29the 1-Wire operation.30 31Similar for a 1-Wire read bit or write bit, which uses the baud-rate32115200, i.e. 8.7 us per bit. The transmitted byte 0x80 is used for a33Write-0 operation (low time 69.6us) and the byte 0xff for Read-0, Read-134and Write-1 (low time 8.7us).35 36The default baud-rate for reset and presence detection is 9600 and for37a 1-Wire read or write operation 115200. In case the actual baud-rate38is different from the requested one, the transmitted byte is adapted39to generate the 1-Wire timing patterns.40 41 42Usage43-----44 45Specify the UART 1-wire bus in the device tree by adding the single child46onewire to the serial node (e.g. uart0). For example:47::48 49 @uart0 {50 ...51 onewire {52 compatible = "w1-uart";53 };54 };55